DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
4.2.5 SPI Boot
Table 4-6 lists the device pins that are configured by the ROM for the SPI boot mode.
Table 4-6. Pins Used in SPI Bootmode
SIGNAL NAME
SPI[0]_SCS[0]
PIN NO.
G29
TYPE
I/O
SPI[0]_D[0] (MISO)
SPI[0]_D[1] (MOSI)
SPI[0]_SCLK
J28
I/O
J27
I/O
N24
I/O
4.2.6 Ethernet PHY Mode Selection
When the EMAC bootmode is selected, via the BTMODE[4:0] pins (see Table 4-1), Table 4-7 shows the
sampled value of BTMODE[9:8] pins and the Ethernet PHY Mode selection.
Table 4-9 shows the signal names (pin functions) and the associated pin numbers selected in each
particular EMAC mode.
Table 4-7. EMAC PHY Mode Selection
ETHERNET PHY MODE
BTMODE[9:8]
SELECTION
00b
01b
10b
11b
MII/GMII
RMII
RGMII
RESERVED
Table 4-8. RGMII Internal Delay Selection
RGMII INTERNAL DELAY
BTMODE[7]
SELECTION
0b
1b
Internal Delay Enabled
Internal Delay Disabled
Table 4-9. Pins Used in EMAC[0] MII/GMII, RGMII, and RMII Boot Modes
SIGNAL NAMES
PIN NO.
MII/GMII
TYPE
RGMII
TYPE
RMII
TYPE
Output
only
AG1
DEFAULT
DEFAULT
EMAC_RMREFCLK
AH1
AH2
AL6
AK1
AK2
AL2
AL3
AK3
AK4
AJ4
AL5
EMAC[0]_MCOL
EMAC[0]_MCRS
I
I
EMAC[0]_RGRXCTL
EMAC[0]_RGRXD[2]
DEFAULT
I
I
EMAC[0]_RMRXD[0]
EMAC[0]_RMRXD[1]
DEFAULT
I
I
EMAC[0]_GMTCLK
EMAC[0]_MRCLK
EMAC[0]_MRXD[0]
EMAC[0]_MRXD[1]
EMAC[0]_MRXD[2]
EMAC[0]_MRXD[3]
EMAC[0]_MRXD[4]
EMAC[0]_MRXD[5]
EMAC[0]_MRXD[6]
O
I
EMAC[0]_RGTXC
EMAC[0]_RGTXD[0]
EMAC[0]_RGRXD[0]
EMAC[0]_RGRXD[1]
DEFAULT
O
O
I
EMAC[0]_RMCRSDV
EMAC[0]_RMTXD[0]
EMAC[0]_RMTXD[1]
EMAC[0]_RMTXEN
DEFAULT
I
I
O
O
O
I
I
I
I
I
EMAC[0]_RGRXD[3]
EMAC[0]_RGTXD[3]
EMAC[0]_RGTXD[2]
I
DEFAULT
I
O
O
DEFAULT
I
DEFAULT
Copyright © 2013, Texas Instruments Incorporated
Device Configurations
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