DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Table 4-9. Pins Used in EMAC[0] MII/GMII, RGMII, and RMII Boot Modes (continued)
SIGNAL NAMES
RGMII
PIN NO.
MII/GMII
TYPE
TYPE
RMII
DEFAULT
DEFAULT
EMAC[0]_RMRXER
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
MDCLK
TYPE
AK5
AJ6
AJ2
AG4
AK6
AJ7
AK7
AE4
AK8
AJ8
AH8
AG8
AF8
AG2
AG3
EMAC[0]_MRXD[7]
EMAC[0]_MRXDV
EMAC[0]_MRXER
EMAC[0]_MTCLK
EMAC[0]_MTXD[0]
EMAC[0]_MTXD[1]
EMAC[0]_MTXD[2]
EMAC[0]_MTXD[3]
EMAC[0]_MTXD[4]
EMAC[0]_MTXD[5]
EMAC[0]_MTXD[6]
EMAC[0]_MTXD[7]
EMAC[0]_MTXEN
MDCLK
I
I
EMAC[0]_RGTXD[1]
DEFAULT
O
I
EMAC[0]_RGTXCTL
EMAC[0]_RGRXC
DEFAULT
O
I
I
I
O
O
O
O
O
O
O
O
O
O
I/O
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
MDCLK
O
O
MDIO
MDIO
I/O
MDIO
I/O
4.2.7 PCIe Bootmode (PCIE_32 and PCIE_64)
Table 4-10 lists the device pins that are configured by the ROM for the PCIe boot mode.
Table 4-10. Pins Used in PCIe Bootmode(1)
SIGNAL NAME
PCIE_TXP0
PIN NO.
L31
TYPE
O
O
I
PCIE_TXN0
K31
PCIE_RXP0
K30
PCIE_RXN0
J30
I
SERDES_CLKP
SERDES_CLKN
H30
I
H31
I
(1) PCIe bootmode is supported on all DM385 devices and also on DM388 devices with PCIe enabled.
PCIe bootmode is not supported on DM388 devices with PCIe disabled.
4.2.8 UART Bootmode
Table 4-11 lists the device pins that are configured by the ROM for the UART boot mode.
Table 4-11. Pins Used in UART Bootmode
SIGNAL NAME
UART0_RXD
PIN NO.
J26
TYPE
I
UART0_TXD
E28
O
114
Device Configurations
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