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DM385 参数 Datasheet PDF下载

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型号: DM385
PDF下载: 下载PDF文件 查看货源
内容描述: DM385和DM388 DaVincia ? ¢数字媒体处理器 [DM385 and DM388 DaVinci™ Digital Media Processor]
分类和应用:
文件页数/大小: 280 页 / 2479 K
品牌: TI [ TEXAS INSTRUMENTS ]
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DM385, DM388  
SPRS821D MARCH 2013REVISED DECEMBER 2013  
www.ti.com  
Table 3-53. Video Input 1 (Digital) Terminal Functions (continued)  
SIGNAL NAME [1]  
VIN[1]A_D[16]  
DESCRIPTION [2]  
TYPE [3]  
AAR BALL [4]  
M11  
Video Input 1 Data inputs. For RGB capture, D[23:16] are  
R Port A data inputs.  
I
VIN[1]A_D[17]  
VIN[1]A_D[18]  
VIN[1]A_D[19]  
VIN[1]A_D[20]  
VIN[1]A_D[21]  
VIN[1]A_D[22]  
VIN[1]A_D[23]  
VIN[1]A_DE  
Video Input 1 Data inputs. For RGB capture, D[23:16] are  
R Port A data inputs.  
I
I
I
I
I
I
I
I
L12  
M10  
J2  
Video Input 1 Data inputs. For RGB capture, D[23:16] are  
R Port A data inputs.  
Video Input 1 Data inputs. For RGB capture, D[23:16] are  
R Port A data inputs.  
Video Input 1 Data inputs. For RGB capture, D[23:16] are  
R Port A data inputs.  
K2  
L2  
Video Input 1 Data inputs. For RGB capture, D[23:16] are  
R Port A data inputs.  
Video Input 1 Data inputs. For RGB capture, D[23:16] are  
R Port A data inputs.  
L4  
Video Input 1 Data inputs. For RGB capture, D[23:16] are  
R Port A data inputs.  
L6  
Video Input 1 Port A Data Enable input. Discrete data  
valid signal for Port A YCbCr capture modes without  
embedded syncs (BT.601 modes).  
F5  
VIN[1]A_FLD  
Video Input 1 Port A Field ID input. Discrete field  
identification signal for Port A YCbCr capture modes  
without embedded syncs (BT.601 modes).  
I
I
F5  
D3  
VIN[1]A_HSYNC  
Video Input 1 Port A Horizontal Sync input. Discrete  
horizontal synchronization signal for Port A YCbCr  
capture modes without embedded syncs (BT.601  
modes).  
VIN[1]A_VSYNC  
VIN[1]B_CLK  
Video Input 1 Port A Vertical Sync input. Discrete vertical  
synchronization signal for Port A YCbCr capture modes  
without embedded syncs (BT.601 modes).  
I
I
E2  
Video Input 1 Port B Clock input. Input clock for 8-bit Port  
B video capture. Input data is sampled on the CLK1  
edge. This signal is not used in 16-bit and 24-bit capture  
modes.  
AF2  
VIN[1]B_D[0]  
VIN[1]B_D[1]  
VIN[1]B_D[2]  
VIN[1]B_D[3]  
VIN[1]B_D[4]  
VIN[1]B_D[5]  
VIN[1]B_D[6]  
VIN[1]B_D[7]  
Video Input Port B Data inputs. For 8-bit capture,  
B_D[7:0] are Port B YCbCr data inputs.  
I
I
I
I
I
I
I
I
AG4  
AH1  
AH2  
AJ2  
AK1  
AK2  
AL2  
AL3  
Video Input Port B Data inputs. For 8-bit capture,  
B_D[7:0] are Port B YCbCr data inputs.  
Video Input Port B Data inputs. For 8-bit capture,  
B_D[7:0] are Port B YCbCr data inputs.  
Video Input Port B Data inputs. For 8-bit capture,  
B_D[7:0] are Port B YCbCr data inputs.  
Video Input Port B Data inputs. For 8-bit capture,  
B_D[7:0] are Port B YCbCr data inputs.  
Video Input Port B Data inputs. For 8-bit capture,  
B_D[7:0] are Port B YCbCr data inputs.  
Video Input Port B Data inputs. For 8-bit capture,  
B_D[7:0] are Port B YCbCr data inputs.  
Video Input Port B Data inputs. For 8-bit capture,  
B_D[7:0] are Port B YCbCr data inputs.  
100  
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Copyright © 2013, Texas Instruments Incorporated  
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