DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
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6.8 Data Transmission Timing Requirements
VBAT = 3.6 ± 5%, TA = 25 ºC, CL = 10 pF (unless otherwise noted)
MIN
0
NOM
MAX
UNIT
MHz
ns
ƒCLK
tCLKL
tCLKH
tt
Serial clock frequency
36
Pulse width low, SPI_CLK, 50% level
Pulse width high, SPI_CLK, 50% level
Transition time, 20% to 80% level, all signals
SPI_CSZ falling to SPI_CLK rising, 50% level
SPI_CLK falling to SPI_CSZ rising, 50% level
SPI_DIN data setup time, 50% level
SPI_DIN data hold time, 50% level
SPI_DOUT data setup time(1), 50% level
SPI_DOUT data hold time(1), 50% level
SPI_CLK falling to SPI_DOUT data valid, 50% level
SPI_CSZ rising to SPI_DOUT HiZ
10
10
0.2
8
ns
4
1
ns
tCSCR
tCFCS
tCDS
tCDH
tiS
ns
ns
7
6
ns
ns
10
0
ns
tiH
ns
tCFDO
tCSZ
13
6
ns
ns
(1) The DPPxxxx processors send and receive data on the falling edge of the clock.
SPI_CSZ
(SS)
tCSCR
tCLKL
tCLKH
tCFCS
SPI_CLK
(SCLK)
tCDS
tCDH
SPI_DIN
(MOSI)
tCFDO
tiH
tCSZ
tiS
SPI_DOUT
(MISO)
HiZ
HiZ
Figure 3. SPI Timing Diagram
12
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