DAC8571
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SLAS373A–DECEMBER 2002–REVISED JULY 2003
THEORY OF OPERATION (continued)
15 V
REF02
5 V
V
, V
DD ref
2-Wire
l C
Interface
A0
V
OUT
= 0 V to 5 V
2
DAC8571
SCL
SDA
Figure 33. REF02 as a Power Supply
5 V
5 kW
160 mA )
+ 1.16 mA
(2)
The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 290 µV for a 1.16-mA
current drawn. This corresponds to a 3.82 LSB error for a 0-V to 5-V output range.
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The power applied to VDD and VREF should be well regulated and low noise. Switching power supplies and dc/dc
converters often has high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise easily
couples into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, VDD is connected to a +5-V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the power entry point. In addition, the 1-µF to 10-µF, and
0.1-µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be required,
such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to
essentially lowpass filter the 5-V supply, removing the high frequency noise.
26
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