DAC1220
www.ti.com...................................................................................................................................... SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009
DIGITAL INTERFACE
Timing
The serial interface is synchronous and controlled by the SCLK input. The DAC1220 latches incoming bits on the
falling edge of SCLK, and shifts outgoing bits on the rising edge of SCLK. An external interface should shift
outgoing bits on the rising edge of SCLK, and latch incoming bits on the falling edge of SCLK. The relevant
waveforms are illustrated in the timing diagrams (see Figure 7 to Figure 11). Timing numbers are given in
Table 2 through Table 4.
tXIN
t1
t2
XIN
Figure 7. XIN Clock Timing
Table 2. XIN Timing Characteristics
SYMBOL
DESCRIPTION
MIN
1
NOM
MAX
2.5
UNITS
MHz
ns
fXIN
tXIN
t1
XIN clock frequency
XIN clock period
XIN clock high
400
1000
0.4 × tXIN
0.4 × tXIN
ns
t2
XIN clock low
ns
t3
t4
t5
SCLK
t6
t7
SDIO
t8
Figure 8. Serial Input/Output Timing
Table 3. Serial I/O Timing Characteristics
SYMBOL
DESCRIPTION
MIN
5 × tXIN
5 × tXIN
40
NOM
MAX
UNITS
ns
t3
t4
t5
t6
t7
t8
SCLK high
SCLK low
ns
Data in valid to SCLK falling edge (setup)
SCLK falling edge to data in not valid (hold)
Data out valid to rising edge of SCLK (hold)
SCLK rising edge to new data out valid (delay)
ns
20
ns
0
ns
50
ns
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