DAC1220
SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
Serial Interface
Most designs will use a single power supply for AVDD
and DVDD. In these designs, the supplies ramp
simultaneously, which is acceptable. In those designs
that use separate sources for AVDD and DVDD, the
two supplies must be sequenced properly. This is
easily done using a Schottky diode, as shown in
Figure 6. The diode ensures that DVDD will not
exceed AVDD by more than a Schottky diode drop.
The DAC1220 can be operated from most SPI
peripherals, or it can be bit-banged.
Note that if SDIO is operated bidirectionally, it may be
necessary to place a pullup resistor on the line, so
that the line will not be floating.
The serial clock is limited to one-tenth of the master
clock frequency. For a 2.4576MHz master clock, the
serial clock may be no faster than 245.76kHz. The
designer should bear this in mind, as it may prevent
the DAC1220 from being shared with other SPI
devices or placed on an SPI bus, which may run
much faster.
Brownouts and Power-On Reset
The DAC1220 incorporates a power-on reset (POR)
circuit. The circuit will trigger as long as the power
supply ramps up at 50mV/ms or faster. If the power
supply ramps more slowly than this, the POR may not
trigger.
If the DAC1220 is placed on a shared SPI bus, the
chip-select line must be controlled; otherwise, it can
be grounded.
The DAC1220 does not have a brownout detector.
The POR circuit will not retrigger unless the supply
voltages have approached ground. Because of this, if
the supply falls to a low voltage, it may corrupt the
logic of the DAC1220, causing it to operate erratically
or to fail entirely. It may be necessary to forcibly
discharge the supply, since the DAC1220 may
occasionally fail to detect the SCLK reset pattern in
this condition.
Although the SDIO line is bidirectional, it can be
operated as an input only, as long as no register
reads are performed. The DAC1220 can be operated
without register reads, although for situations
requiring high reliability, this is not recommended,
since the device registers and operation cannot be
directly verified.
The SCLK reset pattern serves in place of a reset
pin. See the SCLK Reset Pattern section for
information.
Power Supplies
The DAC1220 has separate analog and digital power
supply connections. Both are intended to operate at
+5V.
Supply Decoupling
Both supply pins should be heavily decoupled at the
device for best performance. A 10μF multi-layer
ceramic capacitor can be used for this, or a tantalum
capacitor in parallel with a small (0.1μF) ceramic
capacitor can be used. Both capacitors, particularly
the ceramic capacitor, should be placed as close to
the pins as possible being decoupled.
The digital supply must never exceed the analog
supply by more than 300mV. If it does, the DAC1220
may be permanently damaged. The analog supply
may be greater than the digital supply without
damage, however.
5V
Digital
Supply
DVDD
5V
Analog
Supply
AVDD
Figure 6. Supply Sequence Protection
8
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