DAC1220
SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
t9
t14
SCLK
SDIO
IN7
IN7
IN1
IN1
IN0
INM
IN1
IN0
IN7
IN7
Write Register Data
SDIO
IN0
OUTM
OUT1 OUT0
Read Register Data
Figure 9. Serial Interface Timing (CS Low)
t15
CS
t10
t10
t9
SCLK
IN7
IN1
IN1
IN0
INM
IN1
IN0
IN7
SDIO
SDIO
Write Register Data
IN7
IN0
OUTM
OUT1 OUT0
IN7
Read Register Data
Figure 10. Serial Interface Timing (Using CS)
CS
t11
t12
t10
SCLK
SDIO
t13
IN7
IN0
OUT MSB
OUT0
t9
SDIO is an input
SDIO is an output
Figure 11. SDIO Input to Output Transition Timing
Table 4. Serial Interface Timing Characteristics
SYMBOL
DESCRIPTION
MIN
NOM
MAX
UNITS
ns
Falling edge of last SCLK for command to
rising edge of first SCLK for register data
t9
13 × tXIN
11 × tXIN
8 × tXIN
t10
t11
t12
t13
Falling edge of CS to rising edge of SCLK
ns
Falling edge of last SCLK for command to SDIO as
output
10 × tXIN
ns
SDIO as output to rising edge of first SCLK
for register data
4 × tXIN
ns
ns
Falling edge of last SCLK for register data to SDIO
tri-state
4 × tXIN
6 × tXIN
Falling edge of last SCLK for register data to
rising edge of first SCLK of next command (CS tied
low)
t14
t15
41 × tXIN
22 × tXIN
ns
ns
Rising edge of CS to falling edge of CS (using CS)
10
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