DAC1220
www.ti.com...................................................................................................................................... SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009
The chip-select pin CS is active low. When CS is
high, activity on SCLK is ignored. There are certain
timing limits and delays which apply to the
manipulation of CS, as shown in Figure 10. These
must be observed, or the DAC1220 may malfunction.
SCLK Reset Pattern
The DAC1220 does not have a dedicated reset pin.
Instead, it contains a circuit which waits for a special
pattern to appear on SCLK, and triggers the internal
hardware reset line when it detects the special
pattern.
If CS is not used, it should be tied low. When CS is
tied low, different timing limits and delays must be
observed, as shown in Figure 9. If these are violated,
the DAC1220 may malfunction.
This pattern, called the SCLK reset pattern, is shown
in Figure 12, with timing information given in Table 5.
The pattern is very different from the usual clocking
patterns which appear on SCLK, and is unlikely to be
detected by accident during normal operation.
The serial interface is byte-oriented. All data is
transferred in groups of eight bits.
The SCLK reset pattern can only be triggered when
CS is low. When CS is high, the SCLK line is ignored,
and the SCLK reset pattern is not detected.
I/O Recovery
The DAC1220 has a timeout on the serial interface. If
fCLK is 2.5MHz, the timeout is approximately 100ms.
At 2.5MHz, if a command is interrupted, and no
activity occurs on the SCLK or CS lines for 100ms,
the DAC1220 will cancel the command. If the
command was a write command, no registers are
affected.
The timeout period scales with the frequency of fCLK
.
Reset On
Falling Edge
t17
t17
SCLK
t16
t18
t19
Figure 12. Resetting the DAC1220
Table 5. Reset Timing Characteristics
SYMBOL
DESCRIPTION
MIN
NOM
MAX
UNITS
ns
t16
t17
t18
t19
First high period
Low period
512 × tXIN
10 × tXIN
800 × tXIN
ns
Second high period
Third high period
1024 × tXIN
2048 × tXIN
1800 × tXIN
2400 × tXIN
ns
ns
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