DAC1220
www.ti.com...................................................................................................................................... SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009
Fast Settling Mode
To speed up settling, the DAC1220 can change the
cutoff frequency of its output filter. Raising the cutoff
frequency causes the DAC1220 to settle faster, but at
the expense of higher noise. The adaptive filtering
mode provides a good compromise by increasing the
filter frequency only while the DAC is changing its
output by more than approximately 40mV. When the
output has settled, the filter frequency is reduced
again.
REGISTERS
The register map is shown in Table 11.
Table 11. Register Memory Map
ADDRESS
CONTENT
DIR byte 2 (MSB)
0
1
DIR byte 1
2
DIR byte 0 (LSB)
Reserved
Adaptive filtering is controlled by the ADPT and DISF
bits in the Command Register. The action of these
bits together is described in Table 10.
3
4
CMR byte 1 (MSB)
CMR byte 0 (LSB)
Reserved
5
6
Table 10. Fast Settling Modes
7
Reserved
ADPT
DISF
8
OCR byte 2 (MSB)
OCR byte 1
(CMR bit 15) (CMR bit 4)
FAST SETTLING MODE
9
0
0
Fast settling only during > 40mV
step
10
11
12
13
14
15
OCR byte 0 (LSB)
Reserved
0
1
1
0
Disabled
Fast settling always on (filter cutoff
increased)
FCR byte 2 (MSB)
FCR byte 1
1
1
Disabled
FCR byte 0 (LSB)
Reserved
space
Command Register (CMR)
The command register contains the configuration bits of the DAC1220. It is shown in Table 12. The bits in the
command register are shown in Table 13.
Writes to the CMR take effect at the negative edge of SCLK during the last bit of the last byte of the write
command.
blank
Table 12. Command Register
15
14
13
12
Reserved
R-0
11
Reserved
R-1
10
Reserved
R-0
9
8
ADPT
R/W-0
CALPIN
R/W-0
Reserved
R-1(1)
CRST
R/W-0
Reserved
R-0
(1) In early versions of the DAC1220, this bit was rw-0. See the Calibration section for details.
7
6
5
4
3
2
1
0
RES
R/W-0
CLR
R/W-0
DF
DISF
R/W-0
BD
MSB
R/W-0
MD
R/W-0
R/W-0
R/W-10b
LEGEND: R = Read, W = Write
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