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DAC1220E/2K5G4 参数 Datasheet PDF下载

DAC1220E/2K5G4图片预览
型号: DAC1220E/2K5G4
PDF下载: 下载PDF文件 查看货源
内容描述: 20位,低功耗数位类比转换器 [20-Bit, Low-Power Digital-to-Analog Converter]
分类和应用: 转换器数模转换器光电二极管
文件页数/大小: 26 页 / 622 K
品牌: TI [ TEXAS INSTRUMENTS ]
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DAC1220  
SBAS082G FEBRUARY 1998REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com  
Table 13. Command Register Bits  
BIT(S)  
NAME  
VALUE  
DESCRIPTION  
Controls adaptive filtering. if DISF is set, this bit has no effect.  
Adaptive filtering enabled (default).  
15  
ADPT  
0
1
0
1
Adaptive filtering disabled.  
14  
13  
CALPIN  
Output is disconnected (high impedance) during calibration (default).  
Output is connected during calibration.  
Reserved  
Write '1' to this bit. On early versions of the device, this bit is writable and  
defaults to zero, but still should be set to '1'. On current devices this bit is read-  
only and always reads '1'. See the Calibration section for details.  
12  
11  
10  
9
Reserved  
Reserved  
Reserved  
CRST  
Read-only. Always '0'.  
Read-only. Always '0'.  
Read-only. Always '0'.  
In Normal mode, writing '1' to this bit resets the calibration registers, setting  
OCR to 000000h and FCR to 800000h. In Normal mode, this bit always reads  
'0'.  
In Sleep mode, this bit is read/write, and has no effect.  
Writing '1' to this bit and switching to Normal mode at the same time will reset  
the calibration registers.  
0
1
Do not clear calibration registers.  
Clear calibration registers.  
8
7
Reserved  
RES  
Read-only. Always '0'.  
Selects resolution.  
0
1
16-bit resolution (default).  
20-bit resolution.  
6
CLR  
In Normal mode, writing '1' to this bit writes 0 to the data register.  
In Sleep mode, this bit is read/write, and has no effect.  
Writing '1' to this bit and switching to Normal mode at the same time will reset  
the data register.  
The actual voltage that the DAC1220 will output on setting this bit depends on  
the data format selected by DF. If DF is 1, zero gives 0V; if DF is 0, zero gives  
VREF (mid-scale).  
0
1
Do not clear calibration registers.  
Clear calibration registers.  
5
4
3
DF  
DISF  
BD  
Selects binary number format of the data register.  
Offset two's complement (default).  
0
1
Straight binary.  
Can be used to inhibit fast settling and/or adaptive filtering. See text for details.  
Fast settling and/or adaptive filtering enabled (default).  
Fast settling disabled; filter always at default cutoff.  
0
1
Selects address increment or decrement when reading or writing multiple bytes,  
except when writing to the command register. The command register is always  
written to in increment mode (most significant byte first). Reads from the  
command register are according to this bit.  
0
1
Address is incremented after each byte (default).  
Address is decremented after each byte.  
16  
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Copyright © 1998–2009, Texas Instruments Incorporated  
Product Folder Link(s): DAC1220  
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