DAC1220
SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
APPLICATION INFORMATION
Note that the delays are slightly different if chip-select
(CS) is not being used.
Layout Recommendations
The DAC1220 is a high-precision analog component
Timing delays from the beginning of an SPI byte
incorporating digital elements. Achieving good
transmission
are
a
common
problem
in
precision is not difficult, but achieving excellent
precision may require several attempts.
microcontroller firmware that uses an SPI peripheral.
Be sure that any delay routine begins once a byte
has completed transmission, or add the byte
transmission time to the delay time.
It is critical to supply a guard ring, or fill, around the
C1 and C2 pins. The guard ring should be connected
to the voltage reference. These nodes are very
sensitive, and are good places for noise to couple
through to the output. A ground fill on the opposite
side of the board, or a ground plane, is also a good
idea.
Some programmers may find that bit-banging, or
direct manipulation of microcontroller I/O pins, is the
easiest way to communicate with the DAC1220,
because of the delays and direction changes
required.
The capacitors themselves should be placed as near
the pins as possible. In particular, the traces leading
from C1 and C2 should be kept very short. The traces
leading to VOUT and VREF can be longer.
Write-Only Interfacing
In some situations, such as isolated interfacing, it is
inconvenient to use the DAC1220 bidirectionally,
since the SDIO pin changes direction for readback.
The DAC1220 can be used write-only. The following
considerations apply:
It is also very important to route digital traces away
from analog traces, so that their associated return
currents will not couple into the analog side.
•
When used write-only, it is not possible to verify
that the DAC1220 is operating using its serial
interface alone. The operation of the DAC is
open-loop.
It may be helpful to wait at least 150ms-200ms
after startup. This ensures that, in case the reset
was a result of firmware problems and not
power-up, any previous communication with the
DAC has been cancelled by the I/O recovery
timeout.
When applying the SCLK reset pattern, which can
be done in place of the above steps, allow time for
the oscillator to start before applying the pattern.
The pattern is detected based on oscillator cycles,
so it will not be detected if the oscillator is not yet
running.
If a crystal is used, do not route the traces connecting
the crystal to the device through vias, if possible,
because this will increase the trace inductance and
may affect startup and reliability. Keep the traces
short, and place the crystal close to the device. Keep
in mind that extra ground planes and trace lengths
increase parasitic capacitance, and this should be
deducted from the load capacitor values.
•
Software Considerations
•
A
key to communicating successfully with the
DAC1220 is observing the delays in the interface
timing diagrams. A violation of these delays, at best,
results in lack of correct output; at worse, violating the
delays can corrupt communications entirely.
18
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Product Folder Link(s): DAC1220
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