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DAC1220E/2K5G4 参数 Datasheet PDF下载

DAC1220E/2K5G4图片预览
型号: DAC1220E/2K5G4
PDF下载: 下载PDF文件 查看货源
内容描述: 20位,低功耗数位类比转换器 [20-Bit, Low-Power Digital-to-Analog Converter]
分类和应用: 转换器数模转换器光电二极管
文件页数/大小: 26 页 / 622 K
品牌: TI [ TEXAS INSTRUMENTS ]
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DAC1220  
www.ti.com...................................................................................................................................... SBAS082G FEBRUARY 1998REVISED SEPTEMBER 2009  
Table 13. Command Register Bits (continued)  
BIT(S)  
NAME  
VALUE  
DESCRIPTION  
2
MSB  
Selects the order in which bits are shifted in and out of the DAC1220, except  
when writing to the command register. The command register is always written  
to MSB first. Reads from the command register are according to this bit.  
0
1
Data is shifted MSB first (default).  
Data is shifted LSB first.  
Operating mode.  
1-0  
MD  
00b  
01b  
Normal mode (default).  
Self calibration mode. (No other bits should be changed in the Command  
Register when setting this mode.)  
10b  
11b  
Sleep mode.  
Reserved.  
Data Input Register (DIR)  
The Data Input Register determines the output  
voltage in Normal mode.  
After reset, the OCR contains zero. See the  
Calibration section for further details about the OCR.  
In Sleep mode, writing to this register has no effect  
on the output, but the value is stored. The value in  
the DIR becomes effective immediately upon entering  
Normal mode.  
Full-Scale Calibration Register (FCR)  
The Full-Scale Calibration Register stores the gain  
calibration constant. The content of the DIR is  
adjusted multiplicatively by this value before  
conversion by the DAC.  
After reset, the DIR contains zero.  
See the section, Setting the Output Voltage for further  
details about the Data Input Register.  
In Sleep mode, writing to this register has no effect  
on the output, but the value is stored. The value in  
the FCR becomes effective immediately upon  
entering Normal mode.  
Offset Calibration Register (OCR)  
The Offset Calibration Register contains a 24-bit  
two's complement value. This value is added to the  
value in the DIR before conversion by the DAC.  
After reset, the FCR contains 800000h.  
See the Calibration section for further details about  
the FCR.  
In Sleep mode, writing to this register has no effect  
on the output, but the value is stored. The value in  
the OCR becomes effective immediately upon  
entering Normal mode.  
Copyright © 1998–2009, Texas Instruments Incorporated  
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17  
Product Folder Link(s): DAC1220  
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