CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics
PARAMETER
tPLH
}
tPHL
}
tjit(per)§
( )
tjit(cc)§
( )
Low-to-high level propagation delay time
High-to-low level propagation delay time
Jitter (period) See Figure 5
(period),
Jitter (cycle to cycle) See Figure 2
(cycle-to-cycle),
TEST CONDITIONS
Test mode/CLK to any output
Test mode/CLK to any output
66 MHz
100/133/167/180 MHz
66 MHz
100/133/167/180 MHz
66 MHz
tjit(hper)§
jit(h er)
Half eriod
Half-period jitter, See Figure 6
100 MHz
133/167/180 MHz
Load = 120Ω / 14 pF
tslr(o)
Output clock slew rate See Figure 7
rate,
Load = 120Ω / 4 pF
66 MHz
SSC off
td(Ø)
w
Dynamic phase offset (this includes jitter),
hase
See Figure 3(b)
SSC on
66 MHz
t(Ø)
tsk(o)¶
Static phase offset See Figure 3(a)
offset,
Output skew, See Figure 4
650
100/133/167/180 MHz
100/133 MHz
167/180 MHz
66 MHz
100/133 MHz
167/180 MHz
–55
–35
–60
–50
–130
–90
–75
1
1
–180
–130
–90
–230
–170
–100
–150
–100
MIN
TYP†
4.5
4.5
55
35
60
50
130
90
75
2
3
180
130
90
230
170
100
150
100
50
900
ps
ps
ps
ps
V/ns
V/ns
ps
s
ps
MAX
UNIT
ns
ns
ps
ps
tr, tf
Output rise and fall times (20% – 80%)
Load: 120
Ω/14
pF
† All typical values are at a respective nominal VDDQ.
‡ Refers to transition of noninverting output
§ This parameter is assured by design but can not be 100% production tested.
¶ All differential output pins are terminated with 120
Ω/14
pF.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
TI [ TEXAS INSTRUMENTS ]
