CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
tc(n)
Yx, FBOUT
Yx, FBOUT
1
fo
tjit(per) = tc(n) –
1
fo
Figure 5. Period Jitter
Yx, FBOUT
Yx, FBOUT
t(hper_n)
1
fo
tjit(hper) = t(hper_n) –
1
2xfo
t(hper_n+1)
Figure 6. Half-Period Jitter
80%
Clock Inputs
and Outputs
20%
tslrr(i), tslrr(o)
tslrf(i), tslrf(o)
80%
VID, VOD
20%
Figure 7. Input and Output Slew Rates
8
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