CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
D
Phase-Lock Loop Clock Driver for Double
D
D
D
D
D
D
D
D
D
Data-Rate Synchronous DRAM
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 180 MHz
Low Jitter (cyc–cyc):
±50
ps
Distributes One Differential Clock Input to
Four Differential Clock Outputs
Enters Low Power Mode and Three-State
Outputs When Input CLK Signal Is Less
Than 20 MHz or PWRDWN Is Low
Operates From Dual 2.5-V Supplies
28-Pin TSSOP Package
Consumes < 200-µA Quiescent Current
External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
GND
Y0
Y0
V
DDQ
GND
CLK
CLK
V
DDQ
AV
DD
AGND
V
DDQ
Y1
Y1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PW PACKAGE
(TOP VIEW)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
Y3
Y3
V
DDQ
PWRDWN
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
V
DDQ
Y2
Y2
GND
description
The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of
feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency
with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is
shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below
a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit
detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the
PLL again and enables the outputs.
When AV
DD
is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV855 is characterized for both commercial and
industrial temperature ranges.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
0°C to 70°C
– 40°C to 85°C
TSSOP (PW)
CDCV855PW
CDCV855IPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
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