CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
IOH
IOL
VOD
VOX
II
IOZ
IDD(PD)
Input voltage
All inputs
TEST CONDITIONS
VDDQ = 2.3 V,
II = –18 mA
VDDQ = min to max, IOH = –1 mA
VDDQ = 2.3 V,
IOH = –12 mA
VDDQ = min to max, IOL = 1 mA
VDDQ = 2.3 V,
VDDQ = 2.3 V,
VDDQ = 2.3 V,
IOL = 12 mA
VO = 1 V
VO = 1.2 V
MIN
VDDQ – 0.1
1.7
0.1
0.6
–18
26
1.1
Differential outputs are terminated with
120
Ω
VDDQ = 2.7 V,
VDDQ = 2.7 V,
VI = 0 V to 2.7 V
VO = VDDQ or GND
100
VDDQ/2 – 0.2
VDDQ/2
–32
35
VDDQ – 0.4
VDDQ/2 + 0.2
±10
±10
200
V
µA
µA
µA
V
mA
mA
TYP†
MAX
–1.2
UNIT
V
V
High-level
High level output voltage
Low level output voltage
Low-level
High-level output current
Low-level output current
Output voltage swing
Output differential
cross-voltage
}
Input current
High-impedance-state output
current
Power-down current on
VDDQ + AVDD
CLK and CLK = 0 MHz; PWRDWN = Low;
Σ
of IDD and AIDD
Differential outputs
are terminated with
120
Ω
/ CL = 14 pF
Differential outputs
are terminated with
120
Ω
/ CL = 0 pF
fO = 167 MHz
VDDQ = 2.5 V
150
fO = 167 MHz
130
8
VI = VDDQ or GND
VO = VDDQ or GND
2
2.5
180
mA
160
10
3
mA
pF
IDD
Dynamic current on VDDQ
AIDD
CI
Supply current on AVDD
Input capacitance
CO
Output capacitance
VDDQ = 2.5 V
2.5
3
3.5
pF
† All typical values are at respective nominal VDDQ.
‡ Differential cross-point voltage is expected to track variation of VDDQ and is the voltage at which the differential signals must be crossing.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
fCLK
Operating clock frequency
Input clock duty cycle
Stabilization time (PLL mode)
W
Stabilization time (Bypass mode)
w
MIN
60
40%
MAX
180
60%
10
30
µs
ns
UNIT
MHz
§ Recovery time required when the device goes from power-down mode into bypass mode (test mode with AVDD at GND).
¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
