CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
(Select Functions)
INPUTS
AVDD
GND
GND
X
X
2.5 V (nom)
2.5 V (nom)
2.5 V (nom)
† Typically 10 MHz
PWRDWN
H
H
L
L
H
H
X
CLK
L
H
L
H
L
H
<20 MHz
{
CLK
H
L
H
L
H
L
<20 MHz
{
Y[0:3]
L
H
Z
Z
L
H
Z
H
L
Z
Z
H
L
Z
OUTPUTS
Y[0:3]
FBOUT
L
H
Z
Z
L
H
Z
FBOUT
H
L
Z
Z
H
L
Z
Bypassed/Off
Bypassed/Off
Off
Off
On
On
Off
PLL
functional block diagram
3
2
PWRDWN
AVDD
24
9
Powerdown
and Test
Logic
12
13
17
16
26
27
6
7
23
22
PLL
19
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
CLK
CLK
FBIN
FBIN
FBOUT
20 FBOUT
Terminal Functions
TERMINAL
NAME
AGND
AVDD
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
PWRDWN
VDDQ
Y[0:3]
Y[0:3]
NO.
10
9
6, 7
23, 22
19, 20
1, 5, 14, 15, 28
24
4, 8, 11, 18, 21, 25
3, 12, 17, 26
2, 13, 16, 27
O
O
I
I
I
O
I/O
Ground for 2.5-V analog supply
2.5-V analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Control input to turn device in the power-down mode
2.5-V supply
Buffered output copies of input clock, CLK
Buffered output copies of input clock, CLK
DESCRIPTION
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
