CC1110Fx / CC1111Fx
T1CNTH (0xE3) - Timer 1 Counter High
Bit
Field Name
Reset
R/W
Description
7:0
CNT[15:8]
0x00
R
Timer count high order byte. Contains the high byte of the 16-bit timer counter
buffered at the time T1CNTLis read.
T1CNTL (0xE2) - Timer 1 Counter Low
Bit
Field Name
Reset
R/W
Description
7:0
CNT[7:0]
0x00
R/W
Timer count low order byte. Contains the low byte of the 16-bit timer counter.
Writing anything to this register results in the counter being cleared to 0x0000.
T1CTL (0xE4) - Timer 1 Control and Status
Bit
Field Name
Reset
R/W
Description
7
CH2IF
0
R/W
0
Timer 1 channel 2 interrupt flag
0
1
No interrupt pending
Interrupt pending
6
5
4
CH1IF
CH0IF
OVFIF
0
0
0
R/W
0
Timer 1 channel 1 interrupt flag
0
1
No interrupt pending
Interrupt pending
R/W
0
Timer 1 channel 0 interrupt flag
0
1
No interrupt pending
Interrupt pending
R/W
0
Timer 1 counter overflow interrupt flag. Set when the counter reaches the terminal
count value in free-running or modulo mode or when counter turns around on zero
in up/down mode
0
1
No interrupt pending
Interrupt pending
3:2
DIV[1:0]
00
R/W
Prescaler divider value. Generates the active clock edge used to update the
counter as follows:
00
01
10
11
Tick frequency/1
Tick frequency/8
Tick frequency/32
Tick frequency/128
Note: The prescaler counter is not reset when writing these bits, hence one
prescaler period may be needed before updated data is used.
1:0
MODE[1:0]
00
R/W
Timer 1 mode select. The timer operating mode is selected as follows:
00
01
10
11
Operation is suspended
Free-running, repeatedly count from 0x0000 to 0xFFFF
Modulo, repeatedly count from 0x0000 to T1CC0
Up/down, repeatedly count from 0x0000 to T1CC0 and from T1CC0 down to
0x0000
SWRS033H
Page 120 of 246
TI [ TEXAS INSTRUMENTS ]
