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CC1110F32RHHR 参数 Datasheet PDF下载

CC1110F32RHHR图片预览
型号: CC1110F32RHHR
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的SoC (系统级芯片)与MCU,存储器,低于1GHz的射频收发器和USB控制器 [Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller]
分类和应用: 存储射频控制器
文件页数/大小: 249 页 / 3133 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CC1110Fx / CC1111Fx  
Byte  
Bit  
Field Name  
Description  
Offset  
0
1
2
7:0  
7:0  
7:0  
SRCADDR[15:8]  
SRCADDR[7:0]  
DESTADDR[15:8]  
The DMA channel source address, high byte  
The DMA channel source address, low byte  
The DMA channel destination address, high byte.  
Note that flash memory is not directly writeable.  
The DMA channel destination address, low byte.  
Note that flash memory is not directly writeable.  
Transfer count mode.  
3
4
7:0  
7:5  
DESTADDR[7:0]  
VLEN[2:0]  
000  
001  
010  
011  
100  
101  
110  
111  
Use LENfor transfer count  
Transfer number of bytes/words commanded by n + 1  
Transfer number of bytes/words commanded by n  
Transfer number of bytes/words commanded by n + 2  
Transfer number of bytes/words commanded by n + 3  
Reserved  
Reserved  
Alternative for using LENas transfer count  
Note: For byte size transfers (see Section 12.5.2.4), n is defined as the first byte in  
source data or the 7 LSB of the first byte in source data, depending on the M8  
setting (see Section12.5.2.9). For word size transfers, n is the 13 LSB of the first  
word in source data  
4
5
4:0  
7:0  
LEN[12:8]  
LEN[7:0]  
This value is used as transfer count when VLEN=000or VLEN=111(fixed length  
transfer count). For all cases where VLEN≠000and VLEN≠111 (variable length  
transfer count), the transfer count will be limited to LENbytes/words when n LEN.  
In cases where n < LEN, the transfer count is given by the VLENsetting.  
6
6
7
WORDSIZE  
TMODE[1:0]  
Selects whether each transfer shall be 8-bit (0) or 16-bit (1).  
Transfer mode:  
6:5  
00  
01  
10  
11  
Single  
Block  
Repeated single  
Repeated block  
6
4:0  
TRIG[4:0]  
Select DMA trigger  
00000  
00001  
No trigger (writing to DMAREQ is only trigger)  
The previous DMA channel finished  
00010  
-
Selects one of the triggers shown in Table 51. The trigger is selected in the  
order shown in the table.  
11111  
7
7
7:6  
5:4  
SRCINC[1:0]  
Source address increment mode (after each transfer)  
00  
01  
10  
11  
0 bytes/words  
1 bytes/words  
2 bytes/words  
1 bytes/words  
DESTINC[1:0]  
Destination address increment mode (after each transfer)  
00  
01  
10  
11  
0 bytes/words  
1 bytes/words  
2 bytes/words  
1 bytes/words  
SWRS033H  
Page 108 of 246  
 
 
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