bq3285ED/LD
other pattern to these bits keeps the oscillator off.
pattern of 010 must be set for the bq3285ED/LD to keep
time in battery backup mode.
A
Register A
Register A Bits
7
6
5
4
3
2
1
0
Power-Down/Power-Up Cycle
UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0
The bq3285ED and bq3285LD power-up/power-down cy-
cles are different. The bq3285LD continuously monitors
VCC for out-of-tolerance. During a power failure, when
VCC falls below VPFD (2.53V typical), the bq3285LD write-
protects the clock and storage registers. The power source
is switched to BC when VCC is less than VPFD and BC is
greater than VPFD, or when VCC is less than VBC and VBC
Register A programs:
The frequency of the periodic event rate.
Oscillator operation.
Time-keeping
is less than VPFD. RTC operation and storage data are
Register A provides:
sustained by a valid backup energy source. When VCC is
above VPFD, the power source is VCC. Write-protection con-
Status of the update cycle.
tinues for tCSR time after VCC rises above VPFD
.
RS0–RS3 - Frequency Select
The bq3285ED continuously monitors VCC for out-of-
tolerance. During a power failure, when VCC falls below
VPFD (4.17V typical), the bq3285ED write-protects the
clock and storage registers. When VCC is below VBC (3V
typical), the power source is switched to BC. RTC opera-
tion and storage data are sustained by a valid backup
energy source. When VCC is above VBC, the power
source is VCC. Write-protection continues for tCSR time
7
-
6
-
5
-
4
-
3
2
1
0
RS3 RS2 RS1 RS0
These bits select the periodic interrupt rate, as shown in
Table 3.
OS0–OS2 - Oscillator Control
after VCC rises above VPFD
.
7
-
6
5
4
3
-
2
-
1
-
0
-
Control/Status Registers
OS2 OS1 OS0
The four control/status registers of the bq3285ED/LD
are accessible regardless of the status of the update cy-
cle (see Table 4).
These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC op-
eration by turning on the oscillator and enabling the fre-
quency divider. This pattern must be set to turn the os-
cillator on and to ensure that the bq3285ED/LD keeps
time in battery-backup mode. A pattern of 11X turns the
oscillator on, but keeps the frequency divider disabled.
When 010 is written, the RTC begins its first update af-
ter 500ms.
Table 4. Control/Status Registers
Bit Name and State on Reset
Loc.
Reg. (Hex) Read Write
7 (MSB)
6
5
4
3
2
1
0 (LSB)
A
B
C
D
0A
0B
0C
0D
Yes Yes1 UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na
Yes
Yes
Yes UTI na PIE
0
0
0
AIE
AF
0
0
UIE
UF
0
0
-
-
0
0
DF na HF na DSE na
na
No INTF
0
PF
-
-
-
0
-
0
Yes Yes2 VRT na
DA5 na DA4 na DA3 na DA2 na DA1 na DA0 na
Notes:
na = not affected.
1. Except bit 7.
2. Except bits 6 and 7.
July 1997
8
TI [ TEXAS INSTRUMENTS ]
