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BQ3285LDSSTR 参数 Datasheet PDF下载

BQ3285LDSSTR图片预览
型号: BQ3285LDSSTR
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟(RTC) [Real-Time Clock (RTC)]
分类和应用: 外围集成电路光电二极管时钟
文件页数/大小: 27 页 / 157 K
品牌: TI [ TEXAS INSTRUMENTS ]
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bq3285ED/LD  
Each of the three interrupt events is enabled by an indi-  
vidual interrupt-enable bit in register B. When an event  
occurs, its event flag bit in register C is set. If the corre-  
sponding event enable bit is also set, then an interrupt  
request is generated. The interrupt request flag bit  
(INTF) of register C is set with every interrupt request.  
Reading register C clears all flag bits, including INTF,  
and makes INT high-impedance.  
32kHz Output  
The bq3285ED/LD provides for a 32.768kHz output, and  
the output is always active whenever VCC is valid (VPFD  
+ tCSR). The bq3285ED/LD output is not affected by the  
bit settings in Register A. Time-keeping aspects, how-  
ever, still require setting OS0-OS2.  
Two methods can be used to process bq3285ED/LD in-  
terrupt events:  
Interrupts  
The bq3285ED/LD allows three individually selected in-  
terrupt events to generate an interrupt request. These  
three interrupt events are:  
Enable interrupt events and use the interrupt  
request output to invoke an interrupt service routine.  
The periodic interrupt, programmable to occur once  
Do not enable the interrupts and use  
a polling  
every 122µs to 500ms.  
routine to periodically check the status of the flag  
bits.  
The alarm interrupt, programmable to occur once per  
second to once per day, is active in battery-backup  
mode, providing a wake-up” feature.  
The individual interrupt sources are described in detail  
in the following sections.  
The update-ended interrupt, which occurs at the end  
of each update cycle.  
Table 3. Periodic Interrupt Rate  
Register A Bits  
Periodic Interrupt  
OSC2  
OSC1  
OSC0  
RS3  
0
RS2  
0
RS1  
0
RS0  
0
Period  
None  
3.90625  
Units  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
ms  
ms  
µs  
0
0
1
0
7.8125  
122.070  
244.141  
488.281  
976.5625  
1.95315  
3.90625  
7.8125  
15.625  
31.25  
0
0
1
1
0
1
0
0
µs  
0
1
0
1
µs  
0
1
1
0
µs  
0
1
1
1
ms  
ms  
ms  
ms  
ms  
ms  
ms  
ms  
ms  
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
62.5  
1
1
0
1
125  
1
1
1
0
250  
1
1
1
1
500  
same as above defined  
by RS3–RS0  
0
1
1
X
X
X
X
July 1997  
6
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