bq3285ED/LD
each update period (see Figure 2). The alarm flag bit
may also be set during the update cycle.
Functional Description
The bq3285ED/LD copies the local register updates into
the user buffer accessed by the host processor. When a 1
is written to the update transfer inhibit bit (UTI) in reg-
ister B, the user copy of the clock and calendar bytes re-
mains unchanged, while the local copy of the same bytes
continues to be updated every second.
Address Map
The bq3285ED/LD provides 14 bytes of clock and con-
trol/status registers and 242 bytes of general nonvolatile
storage. Figure 1 illustrates the address map for the
bq3285ED/LD.
The update-in-progress bit (UIP) in register A is set
tBUC time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.
Update Period
The update period for the bq3285ED/LD is one second.
The bq3285ED/LD updates the contents of the clock and
calendar locations during the update cycle at the end of
0
00
0
1
00
Seconds Alarm 01
Seconds
Clock and
Control Status
Registers
16 Bytes
13
14
0D
0E
Minutes
Minutes Alarm
Hours
2
02
03
04
05
3
Storage
Registers
with
BCD
or
Binary
Format
114
Bytes
4
Hours Alarm
5
EXTRAM = 0
6
Day of Week 06
Date of Month 07
127
0
7F
00
7
8
08
09
0A
0B
0C
0D
Month
Year
Storage
Registers
with
9
128
Bytes
10
11
12
13
Register A
EXTRAM = 1
Register B
Register C
Day of Month
Alarm
127
7F
FG328501.eps
Figure 1. Address Map
Update Period
(1 sec.)
UIP
tUC
(Update Cycle)
tBUC
TD3285e1.eps
Figure 2. Update Period Timing and UIP
July 1997
4
TI [ TEXAS INSTRUMENTS ]
