bq29330
www.ti.com
SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
…
…
…
SCLK
…
…
…
…
…
D0
ACK
R/W ACK
A6
A5 A4
A0
R7
R6
R5
R0
D7
D6
D5
SDATA
ACK
0
0
0
0
Data
Start
Slave Address
Register Address
Stop
Note: Slave = bq29330
Figure 5. I2C-Bus Write to bq29330
SCLK
…
…
…
…
NACK
D0
A6
A5
R/W ACK
R7
R6
A6
A0
ACK D7
D6
…
R0
R/W
A0
SDATA
…
…
ACK
0
0
0
1
0
Master
Drives
NACK and
Stop
Slave Drives
Start
Start
Slave Address
Stop
Slave Address
Register Address
The Data
Note: Slave = bq29330
Figure 6. I2C-Bus Read from bq29330: Protocol A
…
…
…
…
SCLK
NACK
D0
A6
A5
A0 R/W ACK
R7
R6
R0 ACK
A6 A5
A0 R/W ACK D7
…
…
…
…
SDATA
0
Master
Drives
Slave Drives
The Data
Slave
Start
Slave Address
Register Address
Start
Stop
Stop
NACK and
Stop
Note: Slave = bq29330
Figure 7. I2C-Bus Read from bq29330: Protocol B
REGISTER MAP
The bq29330 has nine addressable registers. These registers provide status, control, and configuration
information for the battery protection system.
NAME
ADDR
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
TYPE
R
DESCRIPTION
STATUS
Status register
OUTPUT_CONTROL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output pin control from system host and external pin status
State control
STATE_CONTROL
FUNCTION_CONTROL
Function control
CELL _SEL
OLV
Battery cell select for cell translation and balance bypass and select mode for calibration
Overload voltage threshold
OLD
Overload delay time
SCC
Short circuit in charge current threshold voltage and delay
Short circuit in discharge current threshold voltage and delay
SCD
BIT MAP
NAME
ADDR TYPE
B7
0
B6
0
B5
0
B4
ZV
B3
B2
OL
B1
B0
STATUS
0x00
0x01
R
WDF
XZV
SCC
DSG
SCD
OUTPUT_ CONTROL
R/W
0
0
PMS_CHG
GPOD
CHG
LTCLR
18
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