bq29330
www.ti.com
SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
CAL1
CAL0
SELECTED MODE
Cell translation for selected cell (default)
0
0
1
1
0
1
0
1
Offset measurement for selected cell
Monitor the VREF value for gain calibration
Monitor the VREF directly value for gain calibration,
bypassing the translation circuit
CELL_SEL b4-b7 (CB0 – CB3): These 4 bits select the series cell for cell balance bypass path.
CELL_SEL b4 (CB0): This bit enables or disables the bottom series cell balance charge bypass path.
0 =
1 =
Disable bottom series cell balance charge bypass path (default)
Enable bottom series cell balance charge bypass path
CELL_SEL b5 (CB1): This bit enables or disables the second lowest series cell balance charge bypass path.
0 =
1 =
Disable series cell balance charge bypass path (default)
Enable series cell balance charge bypass path
CELL_SEL b6 (CB2): This bit enables or disables the second highest cell balance charge bypass path.
0 =
1 =
Disable series cell balance charge bypass path (default)
Enable series cell balance charge bypass path
CELL_SEL b7 (CB3): This bit enables or disables the highest series cell balance charge bypass path.
0 =
1 =
Disable series cell balance charge bypass path (default)
Enable series cell balance charge bypass path
OLV: Overload Voltage threshold register
OLV REGISTER (0x05)
7
0
6
0
5
0
4
3
2
1
0
OLV4
OLV3
OLV2
OLV1
OLV0
OLV (b4-b0): These four bits select the value of the overload threshold with a default of 0000.
OLV (b5-b7): These bits are not used and should be set to 0.
OLV (b4-b0) configuration bits with corresponding voltage threshold(1)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
–0.050 V
–0.055 V
–0.060 V
–0.065 V
–0.070 V
–0.075 V
–0.080 V
–0.085 V
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
–0.090 V
–0.095 V
–0.100 V
–0.105 V
–0.110 V
–0.115 V
–0.120 V
–0.125 V
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
– 0.130 V
–0.135 V
–0.140 V
–0.145 V
–0.150 V
–0.155 V
–0.160 V
–0.165 V
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
–0.170 V
–0.175 V
–0.180 V
–0.185 V
–0.190 V
–0.195 V
–0.200 V
–0.205 V
(1) If RSNS bit is FUNCTION_CONTROL = 1, then the corresponding voltage threshold is divided by 2.
OLD: Overload Delay time configuration register
OLD REGISTER (0x07)
7
0
6
0
5
0
4
0
3
2
1
0
OLD3
OLD2
OLD1
OLD0
22
TI [ TEXAS INSTRUMENTS ]
