bq29330
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SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
OUTPUT_ CONTROL b1 (DSG): This bit controls the external discharge FET.
0 = Discharge FET is off and is controlled by the system host (default).
1 = Discharge FET is on, and the bq29330 is in normal operating mode.
OUTPUT_ CONTROL b2 (CHG): This bit controls the external charge FET.
0 = Charge FET is off, and is controlled by the system host (default).
1 = Charge FET is on, and the bq29330 is in normal operating mode.
OUTPUT_CONTROL b3(ZV): This bit enables or disables the precharge function.
0 = ZVCHG FET is on, and is controlled by the system host (default).
1 = ZVCHG FET is off, and the bq29330 is in normal operating mode.
OUTPUT_CONTROL b4 (GPOD): This bit enables or disables the GPOD output.
0 = GPOD is high impedance (default).
1 = GPOD output is active (GND).
OUTPUT_CONTROL b5 (PMS_CHG): This bit enables the CHG output for 0-V charge, when PMS terminal is
connected to Pack.
0 = CHG FET is off (When PMS = GND, default).
1 = CHG FET is on by connecting CHG and PACK terminal. (When PMS = PACK, default)
STATE_CONTROL : State control register
STATE_CONTROL REGISTER (0x02)
7
0
6
0
5
0
4
3
2
1
0
RSNS
WDRST
WDDIS
SHIP
SLEEP
The STATE_CTL register controls the outputs of the bq29330 and can be used to clear certain states.
STATE_CONTROL b0 (SLEEP): This bit is used to enter the sleep power mode.
0 = bq29330 exits sleep mode (default).
1 = bq29330 enters the sleep mode.
STATE_CONTROL b1 (SHIP): This bit is used to enter the ship power mode when Pack supply voltage is not
applied.
0 = bq29330 in normal mode (default)
1 = bq29330 enters ship mode when pack voltage is removed.
STATE_CONTROL b2 (WDDIS): This bit is used to enable the watchdog timer.
0 = Watchdog timer enabled (default)
1 = Watchdog timer disabled
STATE_CONTROL b3 (WDRST): This bit is used to enable the reset for GC, when watchdog timer is active.
0 = Reset output is disabled, when watchdog timer is active (default).
1 = 2 Times reset output is enabled, when watchdog timer is active.
STATE_CONTROL b4 (RSNS): This bit sets the OL, SCC, and SCD thresholds into a range suitable for a low
sense resistor value by dividing the OLV, SCCV, and SCDV selected voltage thresholds by 2.
0 = Current protection voltage threshold as programmed (default)
1 = Current protection voltage thresholds divided by 2 as programmed
STATE_CONTROL b6..7 (0): These bits are not used and should be set to 0.
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