bq24296
bq24297
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SLUSBP6A –SEPTEMBER 2013–REVISED OCTOBER 2013
System Status Register REG08
BIT
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VBUS_STAT[1] 00 – Unknown (no input, or DPDM detection incomplete), 01 – USB host, 10 – Adapter port, 11 – OTG
VBUS_STAT[0]
CHRG_STAT[1] 00 – Not Charging, 01 – Pre-charge (<VBATLOWV), 10 – Fast Charging, 11 – Charge Termination Done
CHRG_STAT[0]
DPM_STAT
PG_STAT
0 – Not DPM, 1 – VINDPM or IINDPM
0 – Not Power Good, 1 – Power Good
THERM_STAT
VSYS_STAT
0 – Normal, 1 – In Thermal Regulation
0 – Not in VSYSMIN regulation (BAT>VSYSMIN), 1 – In VSYSMIN regulation (BAT<VSYSMIN)
New Fault Register REG09(1)(2)(3)
BIT
DESCRIPTION
Bit 7
Bit 6
WATCHDOG_FAULT 0 – Normal, 1- Watchdog timer expiration
OTG_FAULT
0 – Normal, 1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low (any conditions that we
cannot start boost function)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CHRG_FAULT[1]
CHRG_FAULT[0]
BAT_FAULT
00 – Normal, 01 – Input fault (OVP or bad source), 10 - Thermal shutdown,
11 – Charge Timer Expiration
0 – Normal, 1 – System OVP
Reserved – 0
Reserved
NTC_FAULT[1]
0-Normal 1–Cold Note: Cold temperature threshold is different based on device operates in buck or
boost mode
Bit 0
NTC_FAULT[0]
0-Normal 1–Hot Note: Hot temperature threshold is different based on device operates in buck or boost
mode
(1) REG09 only supports single byte i2c read.
(2) All register bits in REG09 are latched fault. First time read of REG09 will clear the previous fault and second read will update fault
register to any fault that still presents.
(3) When adapter is unplugged, input fault (bad source) in CHRG_FAULT bits[5:4] will be set to 01 once.
Vender / Part / Revision Status Register REG0A
BIT
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PN[2]
001 (bq24296)
011 (bq24297)
PN[1]
PN[0]
Reserved
Reserved
Rev[2]
Rev[1]
Rev[0]
0 – Reserved
0 – Reserved
000
DETAILED DESCRIPTION
The bq24296, bq24297 is an I2C controlled power path management device and a single cell Li-Ion battery
charger. It integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-
side switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. The device also
integrates the bootstrap diode for the high-side gate drive.
Device Power Up
Power-On-Reset (POR)
The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises
above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface
is ready for communication and all the registers are reset to default value. The host can access all the registers
after POR.
Copyright © 2013, Texas Instruments Incorporated
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