bq24160, bq24161
bq24163, bq24168
SLUSAO0A –NOVEMBER 2011–REVISED MARCH 2012
www.ti.com
BLOCK DIAGRAM
PMIDU
PMIDI
5.2-V Reference
DRV
IN
Q1
USB
5A
BOOT
CbC Current
Limit
IN IINLIM
USB IUSBLIM
IN VINDPM
DC-DC CONVERTER
PWM LOGIC,
COMPENSATION
AND
BATTERY FET CONTROL
Q2
USB VINDPM
VSYS(REG)
IBAT(REG)
SW
VBAT(REG)
DIE Temp
Regulation
Q3
PGND
SYS
VSUPPLY
References
SUPPLY_SEL
+
VUSB
Termination
Reference
VUSBOVP
+
IBAT
OVP Comparators
+
Q4
Termination Comparator
VIN
BAT
VINOVP
Recharge Comparator
+
VBATREG – 0.12V
Start Recharge
Cycle
+
VBAT
VUSB
VSYSREG Comparator
VBAT + VSLP
+
VSYS
Enable Linear
Charge
Sleep Comparators
+
VMINSYS
VIN
+
VBAT
Good Battery
Circuit
VBAT + VSLP
Hi-Z Mode
BGATE
VBATGD
VBATSC Comparator
CD
Hi-Z Mode
+
Enable
IBATSHRT
VBAT
VBATSHRT
SDA
I2C
Interface
Supplement Comparator
+
+
VSYS
SCL
VBAT
VBSUP
VDRV
bq24160/3
VBOVP Comparator
+
USB
VBAT
D+
D–
Adapter
Detection
Circuitry
1.5A/USB100
VBATOVP
+
+
DISABLE
1C/0.5C
TS COLD
TS COOL
bq24161/8
PSEL
bq24160/2/3
+
+
VBATREG – 0.14V
DISABLE
STAT
INT
TS WARM
TS HOT
CHARGE
CONTROLLER
with Timers (160/1/3)
TS
8
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