AM6548, AM6528, AM6526
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021
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6.3.26.2 Clock
6.3.26.2.1 MAIN Domain
表6-68. Clock1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
High frequency oscillator input
BALL [4]
[3]
OSC1_XI
I
C22
E22
OSC1_XO
High frequency oscillator output
O
6.3.26.2.2 WKUP Domain
表6-69. Clock0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
WKUP_LFOSC0_XI
WKUP_LFOSC0_XO
WKUP_OSC0_XI
Low frequency (32.768 kHz) oscillator input
Low frequency (32.768 kHz) oscillator output
High frequency oscillator input
I
AE4
AC4
AD5
AE6
O
I
WKUP_OSC0_XO
High frequency oscillator output
O
6.3.26.3 System
6.3.26.3.1 MAIN Domain
表6-70. System0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
External clock input to Main Domain, routed to Timer
clock muxes as one of the selectable input clock sources
for Timer/WDT modules, or as reference clock to
MAIN_PLL2 (PER1 PLL)
EXT_REFCLK1
I
A22
GPMC functional clock output selected through a mux
logic
GPMC0_FCLK_MUX
NMIn
O
I
R28
F18
C23
External Interrupt
Observation clock output for test and debug purposes
only
OBSCLK0
O
PORz
Main Domain cold reset
I
E19
C19
AF9
AF10
AE8
AE9
D19
F17
PORz_OUT
REFCLK0N
REFCLK0P
REFCLK1N
REFCLK1P
RESETSTATz
RESETz
Main Domain POR status output
O
O
O
O
O
O
I
SERDES Differential Clock Output (negative)
SERDES Differential Clock Output (positive)
SERDES Differential Clock Output (negative)
SERDES Differential Clock Output (positive)
Main Domain warm reset status output
Main Domain warm reset
SOC_SAFETY_ERRORn
Error signal output from Main Domain ESM
IO
E20
SYSCLK0 output from Main PLL controller (divided by 4)
for test and debug purposes only
SYSCLKOUT0
O
B22
6.3.26.3.2 WKUP Domain
表6-71. System0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU Bypass reset circuitry input. 0 = Internal POR is
used, 1 = External MCU_PORz signal is used.
MCU_BYP_POR
I
V5
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