AM6548, AM6528, AM6526
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021
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表6-57. SERDES1 Signal Descriptions (continued)
see (1)
PIN TYPE
SIGNAL NAME [1]
SERDES1_TXP
DESCRIPTION [2]
BALL [4]
[3]
SERDES Differential Transmit Data (positive)
O
AG8
(1) The functionality of these pins is controlled by CTRLMMR_SERDES1_CTRL[1:0] LANE_FUNC_SEL. 0x0 = PCIe1 Lane0, 0x1 =
PCIe0 Lane1, 0x2 = ICSS2 SGMII Lane1.
6.3.23 UART
6.3.23.1 MAIN Domain
表6-58. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
UART0_CTSn
DESCRIPTION [2]
UART Clear to Send (active low)
BALL [4]
[3]
I
AG11
D25
UART0_DCDn
UART0_DSRn
UART0_DTRn
UART0_RIN
UART Data Carrier Detect (active low)
UART Data Set Ready (active low)
UART Data Terminal Ready (active low)
UART Ring Indicator
I
I
B26
O
I
A24
E24
UART0_RTSn
UART0_RXD
UART0_TXD
UART Request to Send (active low)
UART Receive Data
O
I
AD11
AF11
AE11
UART Transmit Data
O
表6-59. UART1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART1_CTSn
UART1_RTSn
UART1_RXD
UART1_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
AD22
AC21
AE23
AD23
O
I
UART Transmit Data
O
表6-60. UART2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART2_CTSn
UART2_RTSn
UART2_RXD
UART2_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
Y26
W26
Y27
W28
O
I
UART Transmit Data
O
6.3.23.2 MCU Domain
表6-61. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_UART0_CTSn
MCU_UART0_RTSn
MCU_UART0_RXD
MCU_UART0_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
P1
N3
P4
P5
O
I
UART Transmit Data
O
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