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AM3356, AM3354, AM3352
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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I/O CELL [13]
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
DDR_D11
SIGNAL NAME [3]
MODE [4]
[5]
STATE [6]
M4
M2
M1
N2
N1
N3
K3
R1
L1
K3
K4
L3
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_dqm0
ddr_dqm1
ddr_dqs0
ddr_dqs1
ddr_dqsn0
ddr_dqsn1
ddr_odt
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
Yes
Yes
Yes
Yes
NA
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
NA
LVCMOS/SSTL/
HSTL
DDR_D12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I/O
I/O
I/O
I/O
O
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
DDR_D13
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
L4
DDR_D14
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
M1
M2
J2
DDR_D15
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
DDR_DQM0
DDR_DQM1
DDR_DQS0
DDR_DQS1
DDR_DQSn0
DDR_DQSn1
DDR_ODT
H
H
L
1
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
O
1
0
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
P1
L1
I/O
I/O
I/O
I/O
O
Z
0
VDDS_DDR /
VDDS_DDR
Yes
Yes
Yes
Yes
NA
LVCMOS/SSTL/
HSTL
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
R2
L2
P2
L2
H
H
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
G1
F2
G1
G4
G2
J4
0
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
DDR_RASn
DDR_RESETn
DDR_VREF
DDR_VTP
ddr_rasn
ddr_resetn
ddr_vref
ddr_vtp
O
H
L
1
0
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
G2
H4
J1
O
0
0
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
A (17) NA
NA
NA
1
NA
NA
0
VDDS_DDR /
VDDS_DDR
NA
NA
NA
8
Analog
(18)
J3
I
NA
H
VDDS_DDR /
VDDS_DDR
NA
NA
Analog
A4
E18
B2
C18
DDR_WEn
ddr_wen
O
VDDS_DDR /
VDDS_DDR
NA
PU/PD
PU/PD
LVCMOS/SSTL/
HSTL
ECAP0_IN_PWM0_OUT
eCAP0_in_PWM0_out
uart3_txd
0
1
2
3
4
5
6
7
0
7
I/O
O
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
4
LVCMOS
spi1_cs1
I/O
I/O
I/O
I
pr1_ecap0_ecap_capin_apwm_o
spi1_sclk
mmc0_sdwp
xdma_event_intr2
gpio0_7
I
I/O
I/O
I/O
A15
C14
EMU0
EMU0
H
H
0
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpio3_7
22
Terminal Description
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