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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
Analog
[5]
STATE [6]
B8
B6
C7
B7
A7
C8
B8
A8
C9
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
0
A (21)
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
NA
NA
NA
NA
NA
25
NA
A11
A8
0
0
0
0
0
0
0
A (20)
A (20)
A (19)
A (19)
A
Z
Z
Z
Z
Z
Z
Z
VDDA_ADC /
VDDA_ADC
25
NA
NA
NA
NA
NA
NA
NA
Analog
VDDA_ADC /
VDDA_ADC
25
Analog
B11
C8
VDDA_ADC /
VDDA_ADC
25
Analog
VDDA_ADC /
VDDA_ADC
25
Analog
B12
A10
A12
VDDA_ADC /
VDDA_ADC
NA
NA
NA
Analog
A
VDDA_ADC /
VDDA_ADC
Analog
A
VDDA_ADC /
VDDA_ADC
Analog
C13
D6
C10
D6
CAP_VBB_MPU
CAP_VBB_MPU
CAP_VDD_RTC
NA
NA
NA
NA
0
A
A
A
A
O
CAP_VDD_RTC
B10
D13
F3
D9
CAP_VDD_SRAM_CORE
CAP_VDD_SRAM_MPU
DDR_A0
CAP_VDD_SRAM_CORE
CAP_VDD_SRAM_MPU
ddr_a0
D11
F3
H
H
H
H
H
H
H
H
H
H
H
H
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
VDDS_DDR /
VDDS_DDR
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/SSTL/
HSTL
J2
H1
E4
C3
C2
B1
D5
E2
D4
C1
F4
F2
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
ddr_a1
ddr_a2
ddr_a3
ddr_a4
ddr_a5
ddr_a6
ddr_a7
ddr_a8
ddr_a9
ddr_a10
ddr_a11
0
0
0
0
0
0
0
0
0
0
0
O
O
O
O
O
O
O
O
O
O
O
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
D1
B3
E5
A2
B1
D2
C3
B2
E2
G4
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
20
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