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ZCE BALL
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
DDR_A12
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
F4
H1
H3
E3
A3
E1
B4
F1
C2
G3
C1
H2
N4
P4
P2
P1
P3
T1
T2
R3
K2
K1
M3
E3
H3
H4
D3
C4
E1
B3
F1
D2
G3
D1
H2
M3
M4
N1
N2
N3
N4
P3
P4
J1
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
ddr_ck
0
O
O
O
O
O
O
O
O
O
O
O
O
H
H
H
H
H
H
H
H
L
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS_DDR /
VDDS_DDR
NA
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/SSTL/
HSTL
DDR_A13
DDR_A14
DDR_A15
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CASn
DDR_CK
DDR_CKE
DDR_CKn
DDR_CSn0
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
ddr_cke
ddr_nck
ddr_csn0
ddr_d0
L
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
H
H
L
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDS_DDR /
VDDS_DDR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS/SSTL/
HSTL
ddr_d1
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d2
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d3
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d4
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d5
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d6
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d7
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d8
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
K1
K2
ddr_d9
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d10
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
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