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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
Table 5-79. Switching Characteristics for McASP(1)
(see Figure 5-87)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
MAX
Cycle time, McASP[x]_AHCLKR and
McASP[x]_AHCLKX
9
tc(AHCLKRX)
20(2)
40
ns
ns
ns
ns
Pulse duration, McASP[x]_AHCLKR and
McASP[x]_AHCLKX high or low
10 tw(AHCLKRX)
11 tc(ACLKRX)
12 tw(ACLKRX)
0.5P - 2.5(3)
0.5P - 2.5(3)
Cycle time, McASP[x]_ACLKR and
McASP[x]_ACLKX
20
40
Pulse duration, McASP[x]_ACLKR and
McASP[x]_ACLKX high or low
0.5P - 2.5(3)
0.5P - 2.5(3)
ACLKR and
ACLKX int
Delay time, McASP[x]_ACLKR and
McASP[x]_ACLKX transmit edge to
McASP[x]_AFSR and
0
2
6
0
2
6
ACLKR and
ACLKX ext in
13.5
18
McASP[x]_AFSX output valid
13 td(ACLKRX-AFSRX)
ns
Delay time, McASP[x]_ACLKR and
McASP[x]_ACLKX transmit edge to ACLKR and
McASP[x]_AFSR and
McASP[x]_AFSX output valid with
Pad Loopback
ACLKX ext
out
2
13.5
2
18
Delay time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output valid
ACLKX int
0
2
6
0
2
6
ACLKX ext in
13.5
18
14 td(ACLKX-AXR)
ns
ns
Delay time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output valid with Pad Loopback
ACLKX ext
out
2
13.5
2
18
Disable time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output high impedance
ACLKX int
0
2
6
0
2
6
ACLKX ext in
13.5
18
15 tdis(ACLKX-AXR)
Disable time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output high impedance with Pad
Loopback
ACLKX ext
out
2
13.5
2
18
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) 50 MHz
(3) P = AHCLKR and AHCLKX period.
Copyright © 2011–2013, Texas Instruments Incorporated
Peripheral Information and Timings
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