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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
5.6.2.3.4.2 One DDR3 Device
A single DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged
as one 16-bit bank.
5.6.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
Figure 5-58 shows the topology of the CK net classes and Figure 5-59 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR3 Differential CK Input Buffer
–
+
Clock Parallel
Terminator
VDDS_DDR
Rcp
A1
A1
A2
A2
AT
AT
Cac
AM335x
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
Figure 5-58. CK Topology for One DDR3 Device
DDR3 Address and Control Input Buffers
Address and Control
Terminator
Rtt
AM335x
Address and Control
Output Buffer
A1
A2
AT
Vtt
Figure 5-59. ADDR_CTRL Topology for One DDR3 Device
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