AM3352BZCZD80 参数 Datasheet PDF下载

型号：	AM3352BZCZD80
PDF下载：	下载PDF文件查看货源
内容描述：	的Sitara AM335x ARM Cortex-A8的微处理器（MPU ） [Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs)]
分类和应用：	微控制器和处理器外围集成电路微处理器时钟
文件页数/大小：	236 页 / 2887 K
品牌：	TI [ TEXAS INSTRUMENTS ]

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

www.ti.com

SPRS717F –OCTOBER 2011–REVISED APRIL 2013

Table 5-22. GPMC and NOR Flash Switching Characteristics—Synchronous Mode⁽²⁾

OPP100

MIN

OPP50

MIN

NO.

PARAMETER

UNIT

MAX

1 / t_c(clk)

Frequency⁽¹⁵⁾, output clock gpmc_clk

Typical pulse duration, output clock gpmc_clk high

Typical pulse duration, output clock gpmc_clk low

Duty cycle error, output clock gpmc_clk

Jitter standard deviation⁽¹⁶⁾, output clock gpmc_clk

Rise time, output clock gpmc_clk

100

0.5P⁽¹²⁾

50 MHz

t_w(clkH)

t_w(clkL)

t_dc(clk)

t_J(clk)

0.5P⁽¹²⁾

-500

0.5P⁽¹²⁾

-500

500

33.33

t_R(clk)

t_F(clk)

Fall time, output clock gpmc_clk

t_R(do)

Rise time, output data gpmc_ad[15:0]

Fall time, output data gpmc_ad[15:0]

t_F(do)

t_d(clkH-csnV)

Delay time, output clock gpmc_clk rising edge to

output chip select gpmc_csn[x]⁽¹¹⁾transition

F⁽⁶⁾- 2.2 F⁽⁶⁾+ 4.5

E⁽⁵⁾- 2.2 E⁽⁵⁾+ 4.5

B⁽²⁾- 4.5 B⁽²⁾+ 2.3

F⁽⁶⁾- 3.2

E⁽⁵⁾- 3.2

F⁽⁶⁾+ 9.5

t_{d(clkH-csnIV)}

t_d(aV-clk)

t_d(clkH-aIV)

t_{d(be[x]nV-clk)}

Delay time, output clock gpmc_clk rising edge to

output chip select gpmc_csn[x]⁽¹¹⁾invalid

E⁽⁵⁾+ 9.5

Delay time, output address gpmc_a[27:1] valid to

output clock gpmc_clk first edge

B⁽²⁾- 5.5 B⁽²⁾+ 12.3

-3.3 14.5

B⁽²⁾- 2.9 B⁽²⁾+ 12.3

Delay time, output clock gpmc_clk rising edge to

output address gpmc_a[27:1] invalid

-2.3

4.5

Delay time, output lower byte enable and command

latch enable gpmc_be0n_cle, output upper byte

enable gpmc_be1n valid to output clock gpmc_clk

first edge

B⁽²⁾- 1.9 B⁽²⁾+ 2.3

t_{d(clkH-be[x]nIV)}

Delay time, output clock gpmc_clk rising edge to

output lower byte enable and command latch enable

gpmc_be0n_cle, output upper byte enable

gpmc_be1n invalid

D⁽⁴⁾- 2.3 D⁽⁴⁾+ 1.9

D⁽⁴⁾- 3.3 D⁽⁴⁾+ 11.9

t_d(clkH-advn)

Delay time, output clock gpmc_clk rising edge to

output address valid and address latch enable

gpmc_advn_ale transition

G⁽⁷⁾- 2.3 G⁽⁷⁾+ 4.5

D⁽⁴⁾- 2.3 D⁽⁴⁾+ 3.5

G⁽⁷⁾- 3.3

D⁽⁴⁾- 3.3

G⁽⁷⁾+ 9.5

D⁽⁴⁾+ 9.5

t_{d(clkH-advnIV)}

Delay time, output clock gpmc_clk rising edge to

output address valid and address latch enable

gpmc_advn_ale invalid

F10

F11

F14

F15

F17

t_d(clkH-oen)

t_{d(clkH-oenIV)}

t_d(clkH-wen)

t_d(clkH-do)

Delay time, output clock gpmc_clk rising edge to

output enable gpmc_oen transition

H⁽⁸⁾- 2.3 H⁽⁸⁾+ 3.5

E⁽⁵⁾- 2.3 E⁽⁵⁾+ 3.5

H⁽⁸⁾- 3.3

E⁽⁵⁾- 3.3

I⁽⁹⁾- 3.3

H⁽⁸⁾+ 8.5

E⁽⁵⁾+ 8.5

I⁽⁹⁾+ 9.5

Delay time, output clock gpmc_clk rising edge to

output enable gpmc_oen invalid

Delay time, output clock gpmc_clk rising edge to

output write enable gpmc_wen transition

I⁽⁹⁾- 2.3

I⁽⁹⁾+ 4.5

Delay time, output clock gpmc_clk rising edge to

output data gpmc_ad[15:0] transition

J⁽¹⁰⁾- 2.3 J⁽¹⁰⁾+ 1.9 J⁽¹⁰⁾- 3.3 J⁽¹⁰⁾+ 11.9

t_{d(clkH-be[x]n)}

Delay time, output clock gpmc_clk rising edge to

output lower byte enable and command latch enable

gpmc_be0n_cle transition

F18

F19

t_w(csnV)

Pulse duration, output chip select

gpmc_csn[x]⁽¹¹⁾low

Read

Write

Read

Write

A⁽¹⁾

C⁽³⁾

A⁽¹⁾

C⁽³⁾

t_w(be[x]nV)

Pulse duration, output lower byte enable

and command latch enable

gpmc_be0n_cle, output upper byte enable

gpmc_be1n low

F20

t_w(advnV)

Pulse duration, output address valid and

address latch enable gpmc_advn_ale low

Read

Write

K⁽¹³⁾

Peripheral Information and Timings

127

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