AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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5.5.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
Table 5-16. Timing Requirements for RGMII[x]_RCLK - RGMII Mode
(see Figure 5-13)
10 Mbps
TYP
100 Mbps
TYP
1000 Mbps
TYP
NO.
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
1
2
tc(RXC)
Cycle time, RXC
360
440
36
44
7.2
8.8 ns
Pulse duration, RXC
high
tw(RXCH)
160
160
240
16
16
24
3.6
3.6
4.4 ns
3
4
tw(RXCL)
tt(RXC)
Pulse duration, RXC low
Transition time, RXC
240
24
4.4 ns
0.75
0.75
0.75 ns
1
4
2
4
3
RGMII[x]_RCLK
Figure 5-13. RGMII[x]_RCLK Timing - RGMII Mode
Table 5-17. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
(see Figure 5-14)
10 Mbps
MIN TYP
100 Mbps
MIN TYP
1000 Mbps
MIN TYP
NO.
UNIT
MAX
MAX
MAX
Setup time, RD[3:0] valid
before RXC high or low
tsu(RD-RXC)
tsu(RX_CTL-RXC)
1
1
1
1
1
1
1
1
1
1
1
1
1
ns
Setup time, RX_CTL valid
before RXC high or low
Hold time, RD[3:0] valid
after RXC high or low
th(RXC-RD)
2
3
ns
ns
Hold time, RX_CTL valid
after RXC high or low
th(RXC-RX_CTL)
tt(RD)
Transition time, RD
0.75
0.75
0.75
0.75
0.75
0.75
tt(RX_CTL)
Transition time, RX_CTL
RGMII[x]_RCLK(A)
1
1st Half-byte
2
2nd Half-byte
RGMII[x]_RD[3:0](B)
RGMII[x]_RCTL(B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
RXERR
3
A. RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet the
respective timing requirements.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the
rising edge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL
carries RXDV on rising edge of RGMII[x]_RCLK and RXERR on falling edge of RGMII[x]_RCLK.
Figure 5-14. RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode
124
Peripheral Information and Timings
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