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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csn[x]
F4
gpmc_a[10:1]
Valid Address
F19
F6
F7
gpmc_be0n_cle
F19
gpmc_be1n
F6
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen
F10
F11
F13
F12
D 0
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-17. GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)
130
Peripheral Information and Timings
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