AM3352BZCZD80 参数 Datasheet PDF下载

型号：	AM3352BZCZD80
PDF下载：	下载PDF文件查看货源
内容描述：	的Sitara AM335x ARM Cortex-A8的微处理器（MPU ） [Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs)]
分类和应用：	微控制器和处理器外围集成电路微处理器时钟
文件页数/大小：	236 页 / 2887 K
品牌：	TI [ TEXAS INSTRUMENTS ]

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

www.ti.com

SPRS717F –OCTOBER 2011–REVISED APRIL 2013

–

H = 0.5 * OEExtraDelay * GPMC_FCLK⁽¹⁴⁾if ((OEOnTime - ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK⁽¹⁴⁾if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK⁽¹⁴⁾if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):

–

Case GpmcFCLKDivider = 0:

–

H = 0.5 * OEExtraDelay * GPMC_FCLK⁽¹⁴⁾

–

Case GpmcFCLKDivider = 1:

–

H = 0.5 * OEExtraDelay * GPMC_FCLK⁽¹⁴⁾if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime

are even)

–

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK⁽¹⁴⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

H = 0.5 * OEExtraDelay * GPMC_FCLK⁽¹⁴⁾if ((OEOffTime - ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK⁽¹⁴⁾if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK⁽¹⁴⁾if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)

(9) For WE falling edge (WE activated):

–

Case GpmcFCLKDivider = 0:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK⁽¹⁴⁾

–

Case GpmcFCLKDivider = 1:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK⁽¹⁴⁾if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime

are even)

–

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK⁽¹⁴⁾if ((WEOnTime - ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):

–

Case GpmcFCLKDivider = 0:

I = 0.5 * WEExtraDelay * GPMC_FCLK

(14)

–

Case GpmcFCLKDivider = 1:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK⁽¹⁴⁾if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime

are even)

–

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK⁽¹⁴⁾if ((WEOffTime - ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)

(10) J = GPMC_FCLK⁽¹⁴⁾

(11) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.

(12) P = gpmc_clk period in ns

(13) For read: K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK⁽¹⁴⁾

For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK⁽¹⁴⁾

(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(15) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the

GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.

(16) The jitter probability density can be approximated by a Gaussian function.

Peripheral Information and Timings

129

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