AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
Table 5-18. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
(see Figure 5-15)
10 Mbps
TYP
100 Mbps
TYP
1000 Mbps
TYP
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
8.8 ns
1
2
tc(TXC)
Cycle time, TXC
360
440
36
44
7.2
Pulse duration, TXC
high
tw(TXCH)
160
160
240
16
16
24
3.6
3.6
4.4 ns
3
4
tw(TXCL)
tt(TXC)
Pulse duration, TXC low
Transition time, TXC
240
24
4.4 ns
0.75
0.75
0.75 ns
1
4
2
4
3
RGMII[x]_TCLK
Figure 5-15. RGMII[x]_TCLK Timing - RGMII Mode
Table 5-19. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
(see Figure 5-16)
10 Mbps
MIN TYP
100 Mbps
MIN TYP
1000 Mbps
MIN TYP
NO.
PARAMETER
UNIT
ns
MAX
0.5
MAX
0.5
MAX
0.5
tsk(TD-TXC)
TD to TXC output skew
TX_CTL to TXC output skew
Transition time, TD
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
1
tsk(TX_CTL-TXC)
0.5
0.5
0.5
tt(TD)
0.75
0.75
0.75
0.75
0.75
0.75
2
ns
tt(TX_CTL)
Transition time, TX_CTL
RGMII[x]_TCLK(A)
1
1
2
RGMII[x]_TD[3:0](B)
RGMII[x]_TCTL(B)
1st Half-byte
2nd Half-byte
TXERR
TXEN
A. The Ethernet MAC and switch implemented in the AM335x device supports internal delay mode, but timing closure
was not performed for this mode of operation. Therefore, the AM335x device does not support internal delay mode.
B. Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on
the rising edge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL
carries TXEN on rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK.
Figure 5-16. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode
Copyright © 2011–2013, Texas Instruments Incorporated
Peripheral Information and Timings
125
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
TI [ TEXAS INSTRUMENTS ]
