AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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5.5.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing
Table 5-13. Timing Requirements for RMII[x]_REFCLK - RMII Mode
(see Figure 5-10)
NO.
MIN
TYP
MAX
20.001
13
UNIT
ns
1
2
3
tc(REF_CLK)
tw(REF_CLKH)
tw(REF_CLKL)
Cycle time, REF_CLK
19.999
Pulse Duration, REF_CLK high
Pulse Duration, REF_CLK low
7
7
ns
13
ns
1
2
RMII[x]_REFCLK
(Input)
3
Figure 5-10. RMII[x]_REFCLK Timing - RMII Mode
Table 5-14. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
(see Figure 5-11)
NO.
MIN
TYP
MAX
UNIT
tsu(RXD-REF_CLK)
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
Setup time, RXD[1:0] valid before REF_CLK
Setup time, CRS_DV valid before REF_CLK
Setup time, RX_ER valid before REF_CLK
Hold time RXD[1:0] valid after REF_CLK
Hold time, CRS_DV valid after REF_CLK
Hold time, RX_ER valid after REF_CLK
1
4
ns
2
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
2
ns
1
2
RMII[x]_REFCLK (input)
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RXER (inputs)
Figure 5-11. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode
122
Peripheral Information and Timings
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