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AM3352BZCZD80 参数 Datasheet PDF下载

AM3352BZCZD80图片预览
型号: AM3352BZCZD80
PDF下载: 下载PDF文件 查看货源
内容描述: 的Sitara AM335x ARM Cortex-A8的微处理器(MPU ) [Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs)]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 236 页 / 2887 K
品牌: TI [ TEXAS INSTRUMENTS ]
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AM3359, AM3358, AM3357  
AM3356, AM3354, AM3352  
SPRS717F OCTOBER 2011REVISED APRIL 2013  
www.ti.com  
5.5 Ethernet Media Access Controller (EMAC) and Switch  
5.5.1 Ethernet MAC and Switch Electrical Data and Timing  
The Ethernet MAC and Switch implemented in the AM335x device supports GMII mode, but the AM335x  
design does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package  
terminals. Therefore, the AM335x device does not support GMII mode. MII mode is supported with the  
remaining GMII signals.  
The AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number  
SPRUH73) and this document may reference internal signal names when discussing peripheral input and  
output signals since many of the AM335x package terminals can be multiplexed to one of several  
peripheral signals. For example, the AM335x terminal names for port 1 of the Ethernet MAC and switch  
have been changed from GMII to MII to indicate their Mode 0 function, but the internal signal is named  
GMII. However, documents that describe the Ethernet switch reference these signals by their internal  
signal name. For a cross-reference of internal signal names to terminal names, see Table 2-7.  
Operation of the Ethernet MAC and switch is not supported for OPP50.  
Table 5-5. Ethernet MAC and Switch Timing Conditions  
TIMING CONDITION PARAMETER  
MIN  
TYP  
MAX  
UNIT  
Input Conditions  
tR  
tF  
Input signal rise time  
Input signal fall time  
1(1)  
1(1)  
5(1)  
5(1)  
ns  
ns  
Output Condition  
CLOAD Output load capacitance  
3
30  
pF  
(1) Except when specified otherwise.  
5.5.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing  
Table 5-6. Timing Requirements for MDIO_DATA  
(see Figure 5-3)  
NO.  
MIN  
TYP  
MAX  
UNIT  
ns  
1
2
tsu(MDIO-MDC) Setup time, MDIO valid before MDC high  
90  
0
th(MDIO-MDC)  
Hold time, MDIO valid from MDC high  
ns  
1
2
MDIO_CLK Output)  
MDIO_DATA (Input)  
Figure 5-3. MDIO_DATA Timing - Input Mode  
Table 5-7. Switching Characteristics for MDIO_CLK  
(see Figure 5-4)  
NO.  
1
PARAMETER  
Cycle time, MDC  
MIN  
400  
160  
160  
TYP  
MAX  
UNIT  
ns  
tc(MDC)  
tw(MDCH)  
tw(MDCL)  
tt(MDC)  
2
Pulse duration, MDC high  
Pulse duration, MDC low  
Transition time, MDC  
ns  
3
ns  
4
5
ns  
118  
Peripheral Information and Timings  
Copyright © 2011–2013, Texas Instruments Incorporated  
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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352  
 
 
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