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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
1
4
2
3
MDIO_CLK
4
Figure 5-4. MDIO_CLK Timing
Table 5-8. Switching Characteristics for MDIO_DATA
(see Figure 5-5)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
td(MDC-MDIO)
Delay time, MDC high to MDIO valid
10
390
ns
1
MDIO_CLK (Output)
MDIO_DATA (Output)
Figure 5-5. MDIO_DATA Timing - Output Mode
5.5.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
Table 5-9. Timing Requirements for GMII[x]_RXCLK - MII Mode
(see Figure 5-6)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
40.004
26
1
2
3
4
tc(RX_CLK)
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Cycle time, RX_CLK
ns
ns
ns
ns
Pulse Duration, RX_CLK high
Pulse Duration, RX_CLK low
Transition time, RX_CLK
140
260
14
26
5
5
1
4
2
3
GMII[x]_RXCLK
4
Figure 5-6. GMII[x]_RXCLK Timing - MII Mode
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Peripheral Information and Timings
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