ADS8284
www.ti.com................................................................................................................................................................................................... SLAS628–MARCH 2009
TIMING REQUIREMENTS
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V
(1) (2) (3)
PARAMETER
MIN TYP
MAX UNIT
t(CONV)
t(ACQ)
t(HOLD)
tpd1
Conversion time
650
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
Acquisition time
320
Sample capacitor hold time
CONVST low to BUSY high
25
40
15
15
tpd2
Propagation delay time, end of conversion to BUSY low
Propagation delay time, start of convert state to rising edge of BUSY
Pulse duration, CONVST low
tpd3
tw1
40
20
20
tsu1
Setup time, CS low to CONVST low
Pulse duration, CONVST high
tw2
CONVST falling edge jitter
10
tw3
tw4
th1
Pulse duration, BUSY signal low
t(ACQ)min
Pulse duration, BUSY signal high
650
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or
BUS18/16 input changes) after CONVST low
40
ns
td1
Delay time, CS low to RD low
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu2
tw5
ten
Setup time, RD high to CS high
Pulse duration, RD low
50
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
20
20
td2
5
10
20
20
50
td3
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid
Pulse duration, RD high
tw6
tw7
th2
Pulse duration, CS high
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
tpd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
0
ns
td4
tsu3
th3
tdis
td5
td6
td7
tsu5
Delay time, BYTE edge to BUS18/16 edge skew
0
10
10
ns
ns
ns
ns
ns
ns
ns
Setup time, BYTE or BUS18/16 transition to RD falling edge
Hold time, BYTE or BUS18/16 transition to RD falling edge
Disable time, RD high (CS high for read cycle) to 3-stated data bus
Delay time, BUSY low to MSB data valid delay
20
0
Delay time, CS rising edge to BUSY falling edge
50
50
Delay time, BUSY falling edge to CS rising edge
BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16
transition setup time, from BUS18/16 to next BUS18/16.
50
ns
tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the
next falling edge of CS (when CS is used to abort).
60
550
ns
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
(3) All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.
Copyright © 2009, Texas Instruments Incorporated
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