SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010
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PIN CONFIGURATION
DW PACKAGE
SOIC-28
(TOP VIEW)
V
IN
AGND1
REF
CAP
AGND2
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+V
ANA
+V
DIG
-V
ANA
BUSY
CS
R/C
DGND
+V
DIG
+V
ANA
NC
(1)
3
4
5
6
7
8
9
10
11
12
13
14
D0 (LSB)
D1
D2
D3
(1)
Not internally connected.
PIN ASSIGNMENTS
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
6
NAME
V
IN
AGND1
REF
CAP
AGND2
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
D3
O
O
O
O
O
O
O
O
O
DIGITAL
I/O
DESCRIPTION
Analog input. Connect via 50Ω to analog input. Full-scale input range is ±10V.
Analog ground. Used internally as ground reference point. Minimal current flow.
Reference input/output. Outputs internal reference of +2.5V nominal. Can also be driven
by external system reference. In both cases, decouple to ground with a 0.1mF ceramic
capacitor.
Reference buffer output. 10mF tantalum capacitor to ground. Nominally +2V.
Analog ground.
Data bit 11. Most significant bit (MSB) of conversion results. Hi-Z state when CS is high,
or when R/C is low, or when a conversion is in progress.
Data bit 10. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 9. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 8. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 7. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 6. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 5. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 4. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Digital ground.
Data bit 3. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
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