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SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010
PIN ASSIGNMENTS (continued)
PIN
NO.
16
17
18
19
20
21
22
23
24
NAME
D2
D1
D0 (LSB)
NC
+V
ANA
+V
DIG
DGND
R/C
CS
I
I
DIGITAL
I/O
O
O
O
DESCRIPTION
Data bit 2. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 1. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high,
or when R/C is low, or when a conversion is in progress.
Not internally connected.
Analog positive supply input. Nominally +5V. Connect directly to pins 21, 27, and 28.
Digital supply input. Nominally +5V. Connect directly to pins 20, 27, and 28.
Digital ground.
Read/Convert input. With CS low, a falling edge on R/C puts the internal sample/hold into
the hold state and starts a conversion. With CS low and no conversion in progress, a
rising edge on R/C enables the output data bits.
Chip select. With R/C low, a falling edge on CS will initiate a conversion. With R/C high
and no conversion in progress, a falling edge on CS will enable the output data bits.
Busy output. Falls when a conversion is started, and remains low until the conversion is
completed and the data are latched into the output register. With CS low and R/C high,
output data will be valid when BUSY rises, so that the rising edge can be used to latch
the data.
Analog negative supply input. Nominally –5V. Decouple to ground with 0.1mF ceramic
and 10vF tantalum capacitors.
Digital supply input. Nominally +5V. Connect directly to pins 20, 21, and 28.
Analog positive supply input. Nominally +5V. Connect directly to pins 20, 21, and 27, and
decouple to ground with 0.1mF ceramic and 10mF tantalum capacitors.
25
BUSY
O
26
27
28
–V
ANA
+V
DIG
+V
ANA
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