ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009
PIN ASSIGNMENTS (CMOS MODE) – ADS62P49/P48 and ADS62P29/P28 (continued)
PIN
NO. OF
PINS
I/O
DESCRIPTION
NAME
NO.
In parallel interface mode, the user has to tie RESET pin permanently high. (SDATA and
SEN are used as parallel control pins in this mode)
The pin has an internal 100 kΩ pull-down resistor.
SCLK
13
1
I
This pin functions as serial interface clock input when RESET is low.
It controls selection of internal or external reference when RESET is tied high. See
Table 4 for detailed information.
The pin has an internal 100-kΩ pull-down resistor.
SDATA
SEN
14
15
1
1
I
I
Serial interface data input.
The pin has an internal 100-kΩ pull-down resistor.
It has no function in parallel interface mode and can be tied to ground.
This pin functions as serial interface enable input when RESET is low.
It controls selection of data format and interface type when RESET is tied high. See
Table 5 for detailed information.
The pin has an internal 100 kΩ pull-up resistor to DRVDD
This pin functions as serial interface register readout, when the <SERIAL READOUT> bit
is enabled.
SDOUT
64
1
O
When <SERIAL READOUT> = 0, this pin forces logic LOW and is not 3-stated.
CTRL1
CTRL2
CTRL3
CLKOUT
35
36
1
1
1
1
I
I
Digital control input pins. Together, they control various power down modes.
37
I
5
O
CMOS output clock
Refer to
DA0-DA13
Figure 13 and
Figure 14
14
O
Channel A ADC output data bits, CMOS levels
DB0-DB13
DRVDD
14
4
O
I
Channel B ADC output data bits, CMOS levels
Output buffer supply
1, 38, 48, 58
39, 49, 59,
PAD
DRGND
4
I
Output buffer ground
Refer to
Figure 13 and
Figure 14
NC
Do not connect
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