ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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9.1.5 Troubleshooting
表 9-1 lists common issues faced when designing with the ADS131M04-Q1 and the corresponding solutions.
This list is not comprehensive.
表9-1. Troubleshooting Common Issues Using the ADS131M04-Q1
ISSUE
POSSIBLE ROOT CAUSE
ADC conversion data are not being read. The Read data after each DRDY falling edge after
two-deep ADC data FIFO overflows and following the recommendations given in the
triggers DRDY one time every two ADC data Collecting Data for the First Time or After a
POSSIBLE SOLUTION
The DRDY pin is toggling at half the
expected frequency.
periods.
Pause in Data Collection section.
The SYNC/RESET pin functions as a
constant synchronization check, rather than a
convert start pin. See the Synchronization
section for more details on the intended
usage of the SYNC/RESET pin.
The F_RESYNC bit is set in the STATUS
word even though this bit was already
cleared.
The SYNC/RESET pin is being toggled
asynchronously to CLKIN.
The entire frame is not being sent to the
ADC. The ADC does not recognize data as
being read.
Read all data words in the output data frame,
including those for channels that are
disabled.
The same ADC conversion data are output
twice before changing.
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