ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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8.6 ADS131M04-Q1 Registers
表 8-12 lists the ADS131M04-Q1 registers. All register offset addresses not listed in 表 8-12 should be
considered as reserved locations and the register contents should not be modified.
表8-12. Register Map
BIT 15
BIT 7
BIT 14
BIT 13
BIT 12
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
RESET
VALUE
ADDRESS
REGISTER
BIT 6
BIT 5
BIT 4
DEVICE SETTINGS AND INDICATORS (Read-Only Registers)
RESERVED
CHANCNT[3:0]
00h
01h
ID
24xxh
0500h
RESERVED
LOCK
F_RESYNC
REG_MAP
CRC_ERR
CRC_TYPE
DRDY3
RESET
DRDY2
WLENGTH[1:0]
STATUS
RESERVED
DRDY1
DRDY0
GLOBAL SETTINGS ACROSS CHANNELS
RESERVED
REGCRC_EN
RX_CRC_EN
TIMEOUT
CRC_TYPE
RESET
WLENGTH[1:0]
02h
03h
04h
06h
07h
08h
MODE
CLOCK
0510h
0F0Eh
0000h
0600h
0000h
0000h
RESERVED
DRDY_SEL[1:0]
DRDY_HiZ
CH1_EN
DRDY_FMT
CH0_EN
RESERVED
CH3_EN
OSR[2:0]
CH2_EN
RESERVED
TBM
PWR[1:0]
RESERVED
RESERVED
PGAGAIN3[2:0]
PGAGAIN1[2:0]
RESERVED
RESERVED
PGAGAIN2[2:0]
PGAGAIN0[2:0]
GAIN1
RESERVED
GC_DLY[3:0]
CD_LEN[2:0]
GC_EN
CD_EN
CFG
CD_ALLCH
CD_NUM[2:0]
CD_TH_MSB[15:8]
THRSHLD_MSB
THRSHLD_LSB
CD_TH_MSB[7:0]
CD_TH_LSB[7:0]
RESERVED
DCBLOCK[3:0]
CHANNEL-SPECIFIC SETTINGS
PHASE0[9:2]
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
CH0_CFG
0000h
0000h
0000h
8000h
0000h
0000h
0000h
0000h
8000h
0000h
0000h
0000h
0000h
8000h
0000h
PHASE0[1:0]
RESERVED
DCBLK0_DIS0
DCBLK1_DIS0
DCBLK2_DIS0
MUX0[1:0]
OCAL0_MSB[15:8]
OCAL0_MSB[7:0]
OCAL0_LSB[7:0]
RESERVED
CH0_OCAL_MSB
CH0_OCAL_LSB
CH0_GCAL_MSB
CH0_GCAL_LSB
CH1_CFG
GCAL0_MSB[15:8]
GCAL0_MSB[7:0]
GCAL0_LSB[7:0]
RESERVED
PHASE1[9:2]
PHASE1[1:0]
RESERVED
MUX1[1:0]
OCAL1_MSB[15:8]
OCAL1_MSB[7:0]
OCAL1_LSB[7:0]
RESERVED
CH1_OCAL_MSB
CH1_OCAL_LSB
CH1_GCAL_MSB
CH1_GCAL_LSB
CH2_CFG
GCAL1_MSB[15:8]
GCAL1_MSB[7:0]
GCAL1_LSB[7:0]
RESERVED
PHASE2[9:2]
PHASE2[1:0]
RESERVED
MUX2[1:0]
OCAL2_MSB[15:8]
OCAL2_MSB[7:0]
OCAL2_LSB[7:0]
RESERVED
CH2_OCAL_MSB
CH2_OCAL_LSB
CH2_GCAL_MSB
CH2_GCAL_LSB
GCAL2_MSB[15:8]
GCAL2_MSB[7:0]
GCAL2_LSB[7:0]
RESERVED
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