ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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8.3.6 ΔΣModulator
The ADS131M04-Q1 uses a delta-sigma (ΔΣ) modulator to convert the analog input voltage to a one's density
modulated digital bit-stream. The ΔΣ modulator oversamples the input voltage at a frequency many times
greater than the output data rate. The modulator frequency, fMOD, of the ADS131M04-Q1 is equal to half the
controller clock frequency, that is, fMOD = fCLKIN / 2.
The output of the modulator is fed back to the modulator input through a digital-to-analog converter (DAC) as a
means of error correction. This feedback mechanism shapes the modulator quantization noise in the frequency
domain to make the noise more dense at higher frequencies and less dense in the band of interest. The digital
decimation filter following the ΔΣ modulator significantly attenuates the out-of-band modulator quantization
noise, allowing the device to provide excellent dynamic range.
8.3.7 Digital Filter
The ΔΣ modulator bitstream feeds into a digital filter. The digital filter is a linear phase, finite impulse response
(FIR), low-pass sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The
digital filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter is
decimated and downsampled, to reduce the rate at which data come out of the modulator (fMOD) to the output
data rate (fDATA). The decimation factor is defined as per 方程式5 and is called the oversampling ratio (OSR).
OSR = fMOD / fDATA
(5)
The OSR is configurable and set by the OSR[2:0] bits in the CLOCK register. There are eight OSR settings in
the ADS131M04-Q1, allowing eight different data rate settings for any given controller clock frequency. 表 8-2
lists the OSR settings and their corresponding output data rates for the nominal CLKIN frequencies mentioned.
The OSR determines the amount of averaging of the modulator output in the digital filter and therefore also the
filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower bandwidth
results in lower noise whereas higher bandwidth results in higher noise. See 表 7-1 for the noise specifications
for various OSR settings.
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